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1. 发明授权

US06368910B1 Method of fabricating ruthenium-based contact plug for memory devices 有权
标题翻译：制造用于存储器件的钌基接触插塞的方法
公开(公告)号：US06368910B1
公开(公告)日：2002-04-09
申请号：US09721796
申请日：2000-11-24
申请人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
发明人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/76877 , H01L23/485 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.
摘要翻译：一种用于制造诸如动态随机存取存储器（DRAM）和铁电随机存取存储器（FRAM）的半导体存储器单元的方法，其具有改善的电容器电极和下面的器件区域之间的接触。它包括以下主要步骤：（1）在晶片表面上形成第一电介质层; （2）在所述第一电介质层中形成至少一个通孔; （3）在通孔中形成钌基塞; 和（4）形成与钌基塞接触的电容器。钌基塞可以由钌金属，导电氧化钌或导电氧化钌和金属钌的叠层制成。该方法允许在不需要屏蔽的情况下制造存储单元，这是在制造过程中保护存储电极不与Si原子反应所需要的。

2. 发明授权

US06563161B2 Memory-storage node and the method of fabricating the same 有权
公开(公告)号：US06563161B2
公开(公告)日：2003-05-13
申请号：US09813993
申请日：2001-03-22
申请人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

3. 发明授权

US06764863B2 Memory-storage node and the method of fabricating the same 有权
标题翻译：存储器节点及其制造方法
公开(公告)号：US06764863B2
公开(公告)日：2004-07-20
申请号：US10387476
申请日：2003-03-14
申请人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
摘要翻译：本发明的存储器存储节点包括半导体衬底，衬底上的第一绝缘层，形成在第一绝缘层内的导电层，以及形成在导电层上的阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。存储器存储节点还包括位于阻挡层上的第一电极，位于第一电极上的电介质层，以及介电层上的第二电极。本发明的存储器存储器的制造方法提供半导体衬底，并在衬底上形成第一绝缘层。在第一绝缘层中形成第一开口，并且在第一开口中设置导电层。然后在第一开口中和导电层上方形成阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。在第一绝缘层和阻挡层之上形成第二绝缘层。在第二绝缘层中形成第二开口以暴露下面的阻挡层的一部分。第一电极形成在第二开口中，并且在第二绝缘层和第一电极上形成电介质层。最后，在电介质层上形成第二电极。

4. 发明授权

US06690054B2 Capacitor 有权
标题翻译：电容器
公开(公告)号：US06690054B2
公开(公告)日：2004-02-10
申请号：US10173596
申请日：2002-06-19
申请人： Jun Lin , Chung-Ming Chu , Toshiya Suzuki , Katsuhiko Hieda
发明人： Jun Lin , Chung-Ming Chu , Toshiya Suzuki , Katsuhiko Hieda
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L28/91
摘要： A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.
摘要翻译：制造电容器的方法包括以下步骤：在衬底上形成金属的下电极; 在下电极上形成氧化物电介质膜的电容器电介质膜; 在电容器电介质膜上沉积金属膜; 在沉积金属膜的步骤之后，在含氢气氛中进行热处理; 以及在进行热处理的步骤之后图案化金属膜以形成金属膜的上电极。因此，改善了上电极和电容器电介质膜之间的粘附性，并且可以提高电容器特性。

5. 发明授权

US08505192B2 Manufacturing method of common mode filter 失效
标题翻译：共模滤波器的制造方法
公开(公告)号：US08505192B2
公开(公告)日：2013-08-13
申请号：US13248075
申请日：2011-09-29
申请人： Chung-Ming Chu
发明人： Chung-Ming Chu
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F27/292 , H01F2017/0066 , Y10T29/49002 , Y10T29/4902 , Y10T29/49208 , Y10T29/5313
摘要： A manufacturing method of common mode filters and a structure of the same are revealed. A common mode choke layer is disposed over a composite substrate and a second magnetic material layer is coated on an upper surface of the common mode choke layer. The common mode choke layer is produced by a wafer-level electrode leading out method and having leading-out terminals on sides thereof. External electrodes are formed on sides of the common mode choke layer by partial cutting, sputtering, lithography and electroplating at wafer level and corresponding to the leading-out terminals. Thereby common mode filters produced are supported more stably. Moreover, the volume is minimized due to inductive coils and external electrodes connected by wafer level packaging. Thus the common mode filters are mass-produced, the cost is down and the defect rate is reduced.
摘要翻译：揭示了共模滤波器的制造方法及其结构。共模扼流层设置在复合基板上，第二磁性材料层涂覆在共模扼流层的上表面上。共模扼流层由晶片级电极引出方法产生，并在其侧面具有引出端子。外部电极通过部分切割，溅射，平版印刷和电镀在晶片级并对应于引出端形成在共模扼流层的侧面上。由此，所产生的共模滤波器更稳定地被支持。此外，由于电感线圈和通过晶片级封装连接的外部电极，体积被最小化。因此，共模滤波器被批量生产，成本下降，缺陷率降低。

6. 发明授权

US06924193B2 Capacitor 有权
标题翻译：电容器
公开(公告)号：US06924193B2
公开(公告)日：2005-08-02
申请号：US10705889
申请日：2003-11-13
申请人： Jun Lin , Chung-Ming Chu , Toshiya Suzuki , Katsuhiko Hieda
发明人： Jun Lin , Chung-Ming Chu , Toshiya Suzuki , Katsuhiko Hieda
IPC分类号： H01L21/28 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/108
CPC分类号： H01L28/60 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L28/91
摘要： A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.
摘要翻译：制造电容器的方法包括以下步骤：在衬底上形成金属的下电极; 在下电极上形成氧化物电介质膜的电容器电介质膜; 在电容器电介质膜上沉积金属膜; 在沉积金属膜的步骤之后在氢含量气氛中进行热处理; 以及在进行热处理的步骤之后图案化金属膜以形成金属膜的上电极。因此，改善了上电极和电容器电介质膜之间的粘附性，并且可以提高电容器特性。

7. 发明授权

US06906377B2 Flash memory cell and fabrication thereof 有权
标题翻译：闪存单元及其制造
公开(公告)号：US06906377B2
公开(公告)日：2005-06-14
申请号：US10250038
申请日：2003-05-30
申请人： Chih-Jung Ni , Chung-Ming Chu , Tu-Hao Yu , Kuo-Chen Wang , Wen-Shun Lo , Haochieh Liu
发明人： Chih-Jung Ni , Chung-Ming Chu , Tu-Hao Yu , Kuo-Chen Wang , Wen-Shun Lo , Haochieh Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.
摘要翻译：描述闪存单元，其包括至少衬底，隧道氧化物层，浮动栅极，绝缘层，控制栅极和栅极间介电层。隧道氧化物层设置在基板上。浮置栅极设置在隧道氧化物层上，由隧道氧化物层上的第一导电层和第一导电层上的第二导电层构成。第二导电层具有比第一导电层的顶表面低的底部，并且具有碗状横截面。绝缘层设置在浮置栅极之间，并且每个控制栅极设置在浮置栅极之间，栅间电介质层之间。

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