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1. 发明申请

US20050162303A1 Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor 有权
标题翻译：控制施加到相变存储器件的写入电流和写入驱动器电路的编程方法
公开(公告)号：US20050162303A1
公开(公告)日：2005-07-28
申请号：US11079198
申请日：2005-03-15
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , H03M3/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the PCM in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持PCM在较高电阻状态下的电阻与PCM在较低电阻状态下的电阻的比率恒定或基本恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

2. 发明授权

US07447092B2 Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature 有权
标题翻译：写入驱动电路，用于根据环境温度控制施加到相变存储器的写入电流
公开(公告)号：US07447092B2
公开(公告)日：2008-11-04
申请号：US11079198
申请日：2005-03-15
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C7/04
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied TO Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the phase change material (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到TO相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持在较高电阻状态下的PCM的电阻与相变材料（PCM）的电阻在较低电阻状态下的比率恒定或基本恒定，而与环境温度无关。可以通过增加，减少或保持复位电流和/或设定电流来保持该比率。

3. 发明授权

US06885602B2 Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor 有权
标题翻译：控制施加到相变存储器件的写入电流和写入驱动器电路的编程方法
公开(公告)号：US06885602B2
公开(公告)日：2005-04-26
申请号：US10921797
申请日：2004-08-20
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , G11C7/04
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the Phase-change Memory (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持在较高电阻状态下的PCM的电阻与相位变化存储器（PCM）的电阻在较低电阻状态下的比率恒定或基本上恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

4. 发明申请

US20050041464A1 PROGRAMMING METHOD OF CONTROLLING THE AMOUNT OF WRITE CURRENT APPLIED TO PHASE CHANGE MEMORY DEVICE AND WRITE DRIVER CIRCUIT THEREFOR 有权
标题翻译：控制适用于相变存储器件和写驱动电路的写电流量的编程方法
公开(公告)号：US20050041464A1
公开(公告)日：2005-02-24
申请号：US10921797
申请日：2004-08-20
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the PCM in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持PCM在较高电阻状态下的电阻与PCM在较低电阻状态下的电阻的比率恒定或基本恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

5. 发明授权

US07391644B2 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US07391644B2
公开(公告)日：2008-06-24
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

6. 发明授权

US07668007B2 Memory system including a resistance variable memory device 有权
标题翻译：存储器系统包括电阻变量存储器件
公开(公告)号：US07668007B2
公开(公告)日：2010-02-23
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

7. 发明申请

US20080232161A1 RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：电阻可变存储器件及其读取方法
公开(公告)号：US20080232161A1
公开(公告)日：2008-09-25
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

8. 发明申请

US20070133271A1 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US20070133271A1
公开(公告)日：2007-06-14
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

9. 发明授权

US07903448B2 Resistance random access memory having common source line 有权
标题翻译：具有共同源极线的电阻随机存取存储器
公开(公告)号：US07903448B2
公开(公告)日：2011-03-08
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Sang-Beom Kang , Joon-Min Park , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

10. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

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