专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070157062A1 Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices 失效
标题翻译：通过扫描子矩阵实现LDPC（低密度奇偶校验）解码器
公开(公告)号：US20070157062A1
公开(公告)日：2007-07-05
申请号：US11360268
申请日：2006-02-23
申请人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/255 , H03M13/27 , H03M13/6362 , H03M13/6566
摘要： Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).
摘要翻译：通过扫描子矩阵实现LDPC（低密度奇偶校验）解码器。提出了一种解码处理与LDPC码对应的低密度奇偶校验矩阵的各个子矩阵的列和行的LDPC编码信号的新方法。低密度奇偶校验矩阵可以根据它的每个子矩阵划分成行和列，并且这些子矩阵中的每一个也包括相应的行和列。例如，当执行位节点处理时，可以一起处理1个或更多个子矩阵的相同列（例如，1个或更多个子矩阵中的所有1个SUP列，全部2个SUP 1个或更多个子矩阵中的 / nd>列等）。类似地，当执行校验节点处理时，可以一起处理1个或更多个子矩阵的相同行（例如，1个或更多个子矩阵中的所有1 ^{行，全部2个 1个或多个子矩阵中的行等）。}

2. 发明申请

US20070157061A1 Sub-matrix-based implementation of LDPC (Low Density Parity Check ) decoder 失效
标题翻译： LDPC（低密度奇偶校验）解码器的基于子矩阵的实现
公开(公告)号：US20070157061A1
公开(公告)日：2007-07-05
申请号：US11360267
申请日：2006-02-23
申请人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/255 , H03M13/27 , H03M13/6362 , H03M13/6566
摘要： Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when performing bit node processing, the sub-matrices in each column are successively processed together (e.g., all column 1 sub-matrices, all column 2 sub-matrices, etc.). Analogously, when performing check node processing, the sub-matrices in each row can be successively processed together (e.g., all row 1 sub-matrices, all row 2 sub-matrices in row 2, etc.).
摘要翻译： LDPC（低密度奇偶校验）解码器的基于子矩阵的实现。提出了一种新颖的方法，通过该方法通过一次处理1个子矩阵对LDPC编码信号进行解码。对应于LDPC码的低密度奇偶校验矩阵包括子矩阵的行和列。例如，当执行位节点处理时，处理列中的一个或多个子矩阵; 当执行校验节点处理时，处理一行中的一个或多个子矩阵。如果需要，当执行位节点处理时，每列中的子矩阵被连续处理（例如，所有列1个子矩阵，全部2个子矩阵等）。类似地，当执行校验节点处理时，可以一起连续地处理每行中的子矩阵（例如，所有行1子矩阵，行2中的所有行2子矩阵等）。

3. 发明申请

US20060156169A1 LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems 有权
标题翻译：在MIMO通信系统中实现的LDPC（低密度奇偶校验）编码和交织
公开(公告)号：US20060156169A1
公开(公告)日：2006-07-13
申请号：US11264998
申请日：2005-11-02
申请人： Ba-Zhong Shen , Christopher Hansen , Joseph Lauer , Kelly Cameron , Tak Lee , Hau Tran
发明人： Ba-Zhong Shen , Christopher Hansen , Joseph Lauer , Kelly Cameron , Tak Lee , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H04L27/2626 , H03M13/1148 , H03M13/116 , H03M13/255 , H03M13/6362 , H04B7/0617 , H04L1/0057 , H04L1/0071 , H04L5/0023 , H04L27/2647 , H04L27/34
摘要： LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. Initially, a novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than regular LDPC codes in terms of providing for lower BER (Bit Error Rate) as a function of SNR (Signal to Noise Ratio). A variety of communication device types are also presented that may employ the error correcting coding using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for even better performance. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
摘要翻译：在多输入多输出（MIMO）通信系统中实现的LDPC（低密度奇偶校验）编码和交织。最初，提出了一种新颖的方法，通过该方法可以使用GRS或RS代码生成各种不规则的LDPC码。在提供作为SNR（信噪比）的函数的较低BER（误码率）方面，这些不规则LDPC码可以提供比常规LDPC码更好的总体性能。还提出了各种通信设备类型，其可以采用基于GRS的不规则LDPC码的纠错编码以及适当选择的交织，以提供更好的性能。这些通信设备可以被实现在无线通信系统中，包括符合由IEEE 802.11n任务组（即，正在努力制定802.11Gn（高吞吐量）的标准的任务组）开发的推荐做法和标准的通信系统，）。

4. 发明申请

US20070127387A1 Partial-parallel implementation of LDPC (low density parity check) decoders 失效
标题翻译： LDPC（低密度奇偶校验）解码器的部分并行实现
公开(公告)号：US20070127387A1
公开(公告)日：2007-06-07
申请号：US11323901
申请日：2005-12-30
申请人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H04J1/16
CPC分类号： H04L1/0052 , H03M13/1111 , H03M13/1137 , H03M13/114 , H03M13/255 , H03M13/27 , H04L1/0057
摘要： Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.
摘要翻译： LDPC（低密度奇偶校验）解码器的部分并行实现。提出了一种新颖的方法，通过该方法在对LDPC编码信号执行纠错解码时，在每个位节点处理和校验节点处理期间执行所选择的周期数。每个位节点处理和校验节点处理的周期数不必相同。可以在比特节点处理和校验节点处理两者期间使用至少一个功能块，组件，硬件部分或计算，从而通过有效利用处理资源来节省空间。至少可以执行在每个位节点处理和校验节点处理期间执行2个周期的半并行方法。或者，可以对比特节点处理和校验节点处理中的每一个执行多于2个周期。

5. 发明申请

US20070033497A1 Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices 失效
公开(公告)号：US20070033497A1
公开(公告)日：2007-02-08
申请号：US11472256
申请日：2006-06-21
申请人： Ba-Zhong Shen , Tak Lee , Kelly Cameron , Hau Tran
发明人： Ba-Zhong Shen , Tak Lee , Kelly Cameron , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1151 , H03M13/1177 , H03M13/1515
摘要： Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

6. 发明申请

US20070033480A1 Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices 失效
标题翻译：具有具有CSI（循环移位标识）子矩阵的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码的有效构造
公开(公告)号：US20070033480A1
公开(公告)日：2007-02-08
申请号：US11472226
申请日：2006-06-21
申请人： Tak Lee , Ba-Zhong Shen , Kelly Cameron , Hau Tran
发明人： Tak Lee , Ba-Zhong Shen , Kelly Cameron , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H03M13/11
摘要： Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
摘要翻译：具有具有CSI（循环移位身份）子矩阵的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码的高效构造。这些构造的LDPC码可以在多输入多输出（MIMO）通信系统中实现。一种LDPC码构造方法使用CSI子矩阵移位值，其移位值被检查，而不是奇偶校验矩阵（或其对应的子矩阵）内的非零元素位置。当设计LDPC码时，该方法在LDPC码的相应二分图中找到并避免周期（或循环）是有效的。另一种方法涉及基于GRS（Generalized Reed-Solomon）代码的LDPC码构造。这些LDPC码可以在各种各样的通信设备中实现，包括在符合由IEEE 802.11n任务组（即正在努力开发的任务组）的建议实践和标准的无线通信系统中实现的通信设备 802.11 TGn（高吞吐量）标准）。

7. 发明申请

US20060156168A1 Construction of irregular LDPC (low density parity check) codes using RS (Reed-Solomon) codes or GRS (generalized Reed-Solomon) code 有权
标题翻译：使用RS（里德 - 所罗门）码或GRS（广义里德 - 所罗门）码构造不规则LDPC（低密度奇偶校验）码
公开(公告)号：US20060156168A1
公开(公告)日：2006-07-13
申请号：US11264997
申请日：2005-11-02
申请人： Ba-Zhong Shen , Kelly Cameron , Tak Lee , Hau Tran
发明人： Ba-Zhong Shen , Kelly Cameron , Tak Lee , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1148 , H03M13/255 , H03M13/6362
摘要： Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. A novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than regular LDPC codes in terms of providing for lower BER (Bit Error Rate) as a function of SNR (Signal to Noise Ratio). Such an irregular LDPC code may be appropriately designed using these principles thereby generating a code that is suitable for use in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE (Institute of Electrical & Electronics Engineers) 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
摘要翻译：使用RS（里德 - 所罗门）代码或GRS（广义里德 - 所罗门）代码构建不规则LDPC（低密度奇偶校验）码。提出了一种新颖的方法，通过该方法可以使用GRS或RS代码生成各种不规则LDPC码。在提供作为SNR（信噪比）的函数的较低BER（误码率）方面，这些不规则LDPC码可以提供比常规LDPC码更好的总体性能。可以使用这些原理来适当地设计这样的不规则LDPC码，从而生成适合于无线通信系统中使用的代码，包括符合IEEE（Institute of Electrical＆Electronics Engineers）802.11n的建议实践和标准的代码任务组（即正在努力制定802.11 TGn（高吞吐量）标准的任务组）。

8. 发明申请

US20080005650A1 LDPC (low density parity check) coded modulation hybrid decoding 有权
标题翻译： LDPC（低密度奇偶校验）编码调制混合解码
公开(公告)号：US20080005650A1
公开(公告)日：2008-01-03
申请号：US11701156
申请日：2007-02-01
申请人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
发明人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
IPC分类号： G06F11/00
CPC分类号： H04L1/005 , H03M13/1105 , H03M13/255 , H04L1/0058
摘要： LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.
摘要翻译： LDPC（低密度奇偶校验）编码调制混合解码。提出了一种新颖的方法，其中对LDPC编码信号执行比特解码和符号级解码（例如混合解码）的组合。对于预定数量的解码迭代，或直到达到足够的精确度，连续替代地对位边消息执行检查节点更新和符号节点更新。位边消息的符号节点更新涉及使用与被解码的符号相对应的符号度量以及最近由校验节点更新更新的位边消息。位边消息的校验节点更新涉及使用最近通过符号节点更新更新的位边消息。符号节点更新还涉及在每次解码迭代期间计算符号的可能的软符号估计。

9. 发明申请

US20060041821A1 Short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications 失效
标题翻译：适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制
公开(公告)号：US20060041821A1
公开(公告)日：2006-02-23
申请号：US11190657
申请日：2005-07-27
申请人： Ba-Zhong Shen , Kelly Cameron , Hau Tran , Scott Powell
发明人： Ba-Zhong Shen , Kelly Cameron , Hau Tran , Scott Powell
IPC分类号： H03M13/00
CPC分类号： H04L27/04 , H03M13/118 , H03M13/255 , H04L25/4917 , H04L27/3416
摘要： A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length-LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.
摘要翻译：适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制。在一些情况下，可以在IEEE 802.3an（10GBASE-T）工作组当前正在开发的推荐做法中采用短长度LDPC码和调制。 IEEE 802.3an（10GBASE-T）工作组已委托开发和标准化通信协议，特别适用于通过4线双绞线电缆进行以太网操作。本文中呈现了新的LDPC码，星座的一些可能的实施例和对应的映射以及LDPC码的各种奇偶校验矩阵H的可能实施例，以提供比本领域中存在的其它提出的LDPC码更好的总体性能的高速以太网应用。此外，该提出的LDPC码可以使用比在该技术空间中存在的其它提出的LDPC码要求更低的复杂度的通信设备进行解码。

10. 发明申请

US20050262421A1 Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 有权
标题翻译：有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理
公开(公告)号：US20050262421A1
公开(公告)日：2005-11-24
申请号：US11171727
申请日：2005-06-30
申请人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/6563 , H03M13/1137 , H03M13/1165
摘要： Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).
摘要翻译：有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理。提出了一种能够对LDPC编码信号进行解码的装置的前端设计有助于LDPC编码信号的并行解码处理的新颖方法。结合执行度量发生器的前端存储器管理的实现协同地借助于LDPC编码信号的非常有效的并行解码处理。存在可以实现前端存储器管理和度量生成器以促进LDPC编码信号的这种并行解码处理的几个实施例。这也允许解码可变码率和/或可变调制信号，其码率和/或调制随着逐个块的频率而变化（例如，一个块可以包括帧内的符号组）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式