专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08502217B2 Oxide semiconductor device including insulating layer and display apparatus using the same 有权
标题翻译：包括绝缘层的氧化物半导体器件和使用其的显示装置
公开(公告)号：US08502217B2
公开(公告)日：2013-08-06
申请号：US12679901
申请日：2008-11-27
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Tomohiro Watanabe
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Tomohiro Watanabe
IPC分类号： H01L29/12 , H01L23/04 , H01L31/036 , H01L31/0376 , H01L27/01
CPC分类号： H01L29/7869 , H01L29/4908 , H01L29/78606
摘要： Provided is an oxide semiconductor device including an oxide semiconductor layer and an insulating layer coming into contact with the oxide semiconductor layer in which the insulating layer includes: a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and including an oxide containing Si and O; a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and including a nitride containing Si and N; and a third insulating layer coming into contact with the second insulating layer, the first insulating layer and the second insulating layer having hydrogen contents of 4×1021 atoms/cm3 or less, and the third insulating layer having a hydrogen content of more than 4×1021 atoms/cm3.
摘要翻译：提供一种氧化物半导体器件，其包括氧化物半导体层和与氧化物半导体层接触的绝缘层，其中绝缘层包括：与氧化物半导体接触的第一绝缘层，其厚度为50nm以上并且包括含有Si和O的氧化物; 与第一绝缘层接触的第二绝缘层，其厚度为50nm以上，并且包括含有Si和N的氮化物; 以及与第二绝缘层接触的第三绝缘层，具有4×1021原子/ cm3以下的氢含量的第一绝缘层和第二绝缘层，以及氢含量大于4× 1021原子/ cm3。

2. 发明申请

US20100283049A1 OXIDE SEMICONDUCTOR DEVICE INCLUDING INSULATING LAYER AND DISPLAY APPARATUS USING THE SAME 有权
标题翻译：包含绝缘层的氧化物半导体器件和使用其的显示器件
公开(公告)号：US20100283049A1
公开(公告)日：2010-11-11
申请号：US12679901
申请日：2008-11-27
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Tomohiro Watanabe
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Tomohiro Watanabe
IPC分类号： H01L33/00 , H01L29/02 , H01L29/786
CPC分类号： H01L29/7869 , H01L29/4908 , H01L29/78606
摘要： Provided is an oxide semiconductor device including an oxide semiconductor layer and an insulating layer coming into contact with the oxide semiconductor layer in which the insulating layer includes: a first insulating layer coming into contact with an oxide semiconductor, having a thickness of 50 nm or more, and including an oxide containing Si and O; a second insulating layer coming into contact with the first insulating layer, having a thickness of 50 nm or more, and including a nitride containing Si and N; and a third insulating layer coming into contact with the second insulating layer, the first insulating layer and the second insulating layer having hydrogen contents of 4×1021 atoms/cm3 or less, and the third insulating layer having a hydrogen content of more than 4×1021 atoms/cm3.
摘要翻译：提供一种氧化物半导体器件，其包括氧化物半导体层和与氧化物半导体层接触的绝缘层，其中绝缘层包括：与氧化物半导体接触的第一绝缘层，其厚度为50nm以上并且包括含有Si和O的氧化物; 与第一绝缘层接触的第二绝缘层，其厚度为50nm以上，并且包括含有Si和N的氮化物; 以及与第二绝缘层接触的第三绝缘层，具有4×1021原子/ cm3以下的氢含量的第一绝缘层和第二绝缘层，以及氢含量大于4× 1021原子/ cm3。

3. 发明申请

US20120032173A1 TOP GATE THIN FILM TRANSISTOR AND DISPLAY APPARATUS INCLUDING THE SAME 有权
标题翻译：顶盖薄膜晶体管和显示装置，包括它们
公开(公告)号：US20120032173A1
公开(公告)日：2012-02-09
申请号：US13188215
申请日：2011-07-21
申请人： Ayumu Sato , Hideya Kumomi , Hisato Yabuta , Ryo Hayashi , Yasuyoshi Takai
发明人： Ayumu Sato , Hideya Kumomi , Hisato Yabuta , Ryo Hayashi , Yasuyoshi Takai
IPC分类号： H01L29/786 , H01L33/16 , H01L29/04
CPC分类号： H01L29/7869 , H01L29/66969 , H01L29/78618 , H01L29/78648
摘要： Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.
摘要翻译：提供了一种顶栅薄膜晶体管，其包括在基板上：源电极层; 漏电极层; 氧化物半导体层; 栅极绝缘层; 包含含有选自In，Ga，Zn和Sn中的至少一种元素的非晶氧化物半导体的栅极电极层; 以及含有氢的保护层，其中：所述栅绝缘层形成在所述氧化物半导体层的沟道区上; 栅电极层形成在栅极绝缘层上; 并且在栅电极层上形成保护层。

4. 发明授权

US08445902B2 Thin film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08445902B2
公开(公告)日：2013-05-21
申请号：US12990408
申请日：2009-04-28
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
IPC分类号： H01L29/10 , H01L29/12
CPC分类号： H01L29/7869 , H01L29/78621
摘要： Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
摘要翻译：提供一种共面结构薄膜晶体管，其制造方法允许阈值电压在电应力下变化很小。薄膜晶体管至少在基板上包括：栅电极; 栅极绝缘层; 包括源电极，漏电极和沟道区的氧化物半导体层; 通道保护层; 和层间绝缘层。沟道保护层包括一层或多层，一层或多层中与氧化物半导体层接触的层由含氧的绝缘材料制成，沟道保护层的端部比通道保护层的中心部分薄层间绝缘层含有氢，与层间绝缘层直接接触的氧化物半导体层的区域形成源电极和漏电极。

5. 发明申请

US20110042670A1 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110042670A1
公开(公告)日：2011-02-24
申请号：US12990408
申请日：2009-04-28
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L29/78621
摘要： Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
摘要翻译：提供一种共面结构薄膜晶体管，其制造方法允许阈值电压在电应力下变化很小。薄膜晶体管至少在基板上包括：栅电极; 栅极绝缘层; 包括源电极，漏电极和沟道区的氧化物半导体层; 通道保护层; 和层间绝缘层。沟道保护层包括一层或多层，一层或多层中与氧化物半导体层接触的层由含氧的绝缘材料制成，沟道保护层的端部比通道保护层的中心部分薄层间绝缘层含有氢，与层间绝缘层直接接触的氧化物半导体层的区域形成源电极和漏电极。

6. 发明授权

US08624240B2 Top gate thin film transistor and display apparatus including the same 有权
标题翻译：顶栅薄膜晶体管和包括其的显示装置
公开(公告)号：US08624240B2
公开(公告)日：2014-01-07
申请号：US13188215
申请日：2011-07-21
申请人： Ayumu Sato , Hideya Kumomi , Hisato Yabuta , Ryo Hayashi , Yasuyoshi Takai
发明人： Ayumu Sato , Hideya Kumomi , Hisato Yabuta , Ryo Hayashi , Yasuyoshi Takai
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L29/66969 , H01L29/78618 , H01L29/78648
摘要： Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.
摘要翻译：提供了一种顶栅薄膜晶体管，其包括在基板上：源电极层; 漏电极层; 氧化物半导体层; 栅极绝缘层; 包含含有选自In，Ga，Zn和Sn中的至少一种元素的非晶氧化物半导体的栅极电极层; 以及含有氢的保护层，其中：所述栅绝缘层形成在所述氧化物半导体层的沟道区上; 栅电极层形成在栅极绝缘层上; 并且在栅电极层上形成保护层。

7. 发明申请

US20110073856A1 THIN FILM TRANSISTOR 有权
标题翻译：薄膜晶体管
公开(公告)号：US20110073856A1
公开(公告)日：2011-03-31
申请号：US12891704
申请日：2010-09-27
申请人： Ayumu Sato , Hideya Kumomi , Ryo Hayashi , Tomohiro Watanabe
发明人： Ayumu Sato , Hideya Kumomi , Ryo Hayashi , Tomohiro Watanabe
IPC分类号： H01L29/786 , H01L29/04 , H01L21/84
CPC分类号： H01L29/7869
摘要： To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.
摘要翻译：为了在氧化物半导体薄层晶体管中实现阈值电压对电应力的稳定性和抑制传输特性中阈值电压变化的两者。薄膜晶体管包括氧化物半导体层和设置成与氧化物半导体层接触的栅极绝缘层，其中氧化物半导体层包含氢原子，并且包括至少两个用作氧化物半导体的有源层的区域并且在层厚度方向上具有不同的平均氢浓度; 并且当用作氧化物半导体的有源层的区域依次定义为从栅极绝缘层的侧面开始第一区域和第二区域时，第一区域的平均氢浓度低于平均氢浓度的第二个地区。

8. 发明授权

US08344373B2 Thin film transistor 有权
标题翻译：薄膜晶体管
公开(公告)号：US08344373B2
公开(公告)日：2013-01-01
申请号：US12891704
申请日：2010-09-27
申请人： Ayumu Sato , Hideya Kumomi , Ryo Hayashi , Tomohiro Watanabe
发明人： Ayumu Sato , Hideya Kumomi , Ryo Hayashi , Tomohiro Watanabe
IPC分类号： H01L29/786 , H01L21/84
CPC分类号： H01L29/7869
摘要： To achieve, in an oxide semiconductor thin layer transistor, both the stability of threshold voltage against electric stress and suppression of variation in the threshold voltage in a transfer characteristic. A thin film transistor includes an oxide semiconductor layer and a gate insulating layer disposed so as to be in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer contains hydrogen atoms and includes at least two regions that function as active layers of the oxide semiconductor and have different average hydrogen concentrations in the layer thickness direction; and when the regions functioning as the active layers of the oxide semiconductor are sequentially defined as, from the side of the gate insulating layer, a first region and a second region, the average hydrogen concentration of the first region is lower than the average hydrogen concentration of the second region.
摘要翻译：为了在氧化物半导体薄层晶体管中实现阈值电压对电应力的稳定性和抑制传输特性中阈值电压变化的两者。薄膜晶体管包括氧化物半导体层和设置成与氧化物半导体层接触的栅极绝缘层，其中氧化物半导体层包含氢原子，并且包括至少两个用作氧化物半导体的有源层的区域并且在层厚度方向上具有不同的平均氢浓度; 并且当用作氧化物半导体的有源层的区域依次定义为从栅极绝缘层的侧面开始第一区域和第二区域时，第一区域的平均氢浓度低于平均氢浓度的第二个地区。

9. 发明授权

US09425056B2 Method for producing silicon wafer 有权
标题翻译：硅晶片的制造方法
公开(公告)号：US09425056B2
公开(公告)日：2016-08-23
申请号：US13983964
申请日：2012-02-09
申请人： Takuya Sasaki , Hiromasa Hashimoto , Kazuya Sato , Ayumu Sato
发明人： Takuya Sasaki , Hiromasa Hashimoto , Kazuya Sato , Ayumu Sato
IPC分类号： H01L21/302 , B24B1/00 , B24B37/08 , H01L21/304 , B24B37/24 , H01L21/02
CPC分类号： H01L21/304 , B24B37/08 , B24B37/24 , H01L21/02024
摘要： The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-C rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.
摘要翻译：本发明提供一种硅晶片的制造方法，其特征在于，具有以下步骤：在原料硅晶片的一个表面上通过化学气相沉积生长氧化膜之后，对所述原料硅晶片进行双面抛光对于氧化膜表面使用具有50°以上且小于90°的Asker-C橡胶硬度的绒面抛光垫或丝绒抛光垫。

10. 发明申请

US20130316521A1 METHOD FOR PRODUCING SILICON WAFER 有权
标题翻译：生产硅波的方法
公开(公告)号：US20130316521A1
公开(公告)日：2013-11-28
申请号：US13983964
申请日：2012-02-09
申请人： Takuya Sasaki , Hiromasa Hashimoto , Kazuya Sato , Ayumu Sato
发明人： Takuya Sasaki , Hiromasa Hashimoto , Kazuya Sato , Ayumu Sato
IPC分类号： H01L21/304
CPC分类号： H01L21/304 , B24B37/08 , B24B37/24 , H01L21/02024
摘要： The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-C rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.
摘要翻译：本发明提供一种硅晶片的制造方法，其特征在于，具有以下步骤：在原料硅晶片的一个表面上通过化学气相沉积生长氧化膜之后，对所述原料硅晶片进行双面抛光对于氧化膜表面使用具有50°以上且小于90°的Asker-C橡胶硬度的绒面抛光垫或丝绒抛光垫。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式