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1. 发明申请

US20060107120A1 Microprocessor design support for computer system and platform validation 失效
公开(公告)号：US20060107120A1
公开(公告)日：2006-05-18
申请号：US11300423
申请日：2005-12-15
申请人： Ayman Abdo , Cameron McNairy , Piyush Desai , Quinn Merrell
发明人： Ayman Abdo , Cameron McNairy , Piyush Desai , Quinn Merrell
IPC分类号： G06F11/00
CPC分类号： G06F11/24 , G06F11/27
摘要： Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

2. 发明授权

US5829038A Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure 失效
标题翻译：在微处理器分级缓存结构中从更高级缓存驱逐修改的行之前向下查询低层缓存
公开(公告)号：US5829038A
公开(公告)日：1998-10-27
申请号：US670253
申请日：1996-06-20
申请人： Quinn Merrell , Wen-Hann Wang
发明人： Quinn Merrell , Wen-Hann Wang
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0811 , G06F12/0804
摘要： A system and method for reducing the number of writeback operations performed by level two (L2) or higher level cache memories in a microprocessor system having an integrated hierarchical cache structure. Writeback operations of modified victim lines in L2 or higher level caches are cancelled if an associated cache line, having a "modified" status, is located in a lower level cache. In one embodiment of the present invention, writeback operations of modified victim lines in L2 or higher level caches are also cancelled if an associated cache line, having a "clean" status, is located in a lower level cache.
摘要翻译：一种用于减少在具有集成分层高速缓存结构的微处理器系统中由二级（L2）或更高级高速缓存存储器执行的回写操作的数量的系统和方法。如果具有“修改”状态的相关联的高速缓存线位于较低级缓存中，则将取消L2或更高级别高速缓存中修改的受害者线路的回写操作。在本发明的一个实施例中，如果具有“干净”状态的相关联的高速缓存线位于较低级别的高速缓存中，那么也将取消L2或更高级别高速缓存中修改的受害线路的回写操作。

3. 发明授权

US06651145B1 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies 有权
标题翻译：在共享存储层次中可扩展消除一致性的方法和装置
公开(公告)号：US06651145B1
公开(公告)日：2003-11-18
申请号：US09677122
申请日：2000-09-29
申请人： Sujat Jamil , Hang Nguyen , Quinn Merrell
发明人： Sujat Jamil , Hang Nguyen , Quinn Merrell
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0811
摘要： Scalable disambiguating accesses in multi-level cache hierarchies provides for improved system performance and reduced cost. Shared-storage provides portions to hold data and portions to hold corresponding status encodings. Status encodings provide information to disambiguate data requests to shared-storage without resorting to prior methods of snooping or transmitting backward status-inquiries to private-storage. Shared-storage transmits data in response to requests if its status encodings indicate no private copies of the requested data have been modified. Shared storage transmits data requests to private storage if corresponding status encodings indicate that copies of requested data in private storage have been modified. Private-storage provides coherent copies, and shared-storage proceeds to satisfy the requests. If requests indicate a need to modify data, shared storage provides invalidation transmissions to private storage holding copies of relevant data. Status encodings are then set to a dirty status for coherently processing future requests.
摘要翻译：多级缓存层级中的可扩展消除歧义访问提供了改进的系统性能并降低了成本。共享存储提供部分来保存数据和部分以保存对应的状态编码。状态编码提供信息，以消除对共享存储的数据请求的歧义，而无需采用先前的侦听方式或将后向状态查询发送到私有存储。共享存储器如果其状态编码指示没有修改所请求数据的私有副本，则响应于请求发送数据。如果对应的状态编码表明私有存储器中所请求的数据的副本已被修改，共享存储将数据请求发送到私有存储。私有存储提供一致的副本，并且共享存储进行以满足请求。如果请求指示需要修改数据，则共享存储向存储相关数据副本的私人存储提供无效传输。然后将状态编码设置为脏状态，以便连贯地处理未来的请求。

4. 发明授权

US07003632B2 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies 有权
公开(公告)号：US07003632B2
公开(公告)日：2006-02-21
申请号：US10620629
申请日：2003-07-15
申请人： Sujat Jamil , Hang Nguyen , Quinn Merrell
发明人： Sujat Jamil , Hang Nguyen , Quinn Merrell
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0811
摘要： Scalable disambiguating accesses in multi-level cache hierarchies provides for improved system performance and reduced cost. Shared-storage provides portions to hold data and portions to hold corresponding status encodings. Status encodings provide information to disambiguate data requests to shared-storege without resorting to prior methods of snooping or transmitting backward status-inquiries to private-storage. Shared-storage transmits data in response to requests if its status encodings indicate no private copies of the requested data have been modified. Shared storage transmits data requests to private storage if corresponding status encodings indicate that copies of requested data in private storage have been modified. Private-storage provides coherent copies, and shared-storage proceeds to satisfy the requests. If requests indicate a need to modify data, shared storage provides invalidation transmissions to private storage holding copies of relevant data. Status encodings are then set to a dirty status for coherently processing future requests.

5. 发明申请

US20060143409A1 Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput 有权
标题翻译：用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置
公开(公告)号：US20060143409A1
公开(公告)日：2006-06-29
申请号：US11027649
申请日：2004-12-29
申请人： Quinn Merrell , R. O'Bleness , Sujat Jamil , Hang Nguyen
发明人： Quinn Merrell , R. O'Bleness , Sujat Jamil , Hang Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating frequency of the cache is higher than the operating frequency of the processor.
摘要翻译：公开了一种用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置。在一个实施例中，装置包括高速缓存，处理器和频率控制器。频率控制器将以高功率模式操作该设备，其中高速缓存的工作频率高于处理器的工作频率。

6. 发明申请

US20060143397A1 Dirty line hint array for cache flushing 审中-公开
标题翻译：用于缓冲区冲洗的脏线提示数组
公开(公告)号：US20060143397A1
公开(公告)日：2006-06-29
申请号：US11027637
申请日：2004-12-29
申请人： R. O'Bleness , Sujat Jamil , Quinn Merrell , Hang Nguyen
发明人： R. O'Bleness , Sujat Jamil , Quinn Merrell , Hang Nguyen
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G06F12/0891
摘要： Techniques for using a dirty line hint array when flushing a cache are disclosed. In one embodiment, an apparatus includes a number of hint bits. Each hint bit corresponds to a number of cache lines, and indicates whether at least one of those cache lines is dirty.
摘要翻译：公开了在刷新缓存时使用脏行提示数组的技术。在一个实施例中，装置包括多个提示位。每个提示位对应于多个高速缓存行，并且指示这些高速缓存行中的至少一个是否是脏的。

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