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1. 发明申请

US20070162672A1 Method and apparatus for fixed latency subtractive decoding 有权
标题翻译：用于固定延迟减法解码的方法和装置
公开(公告)号：US20070162672A1
公开(公告)日：2007-07-12
申请号：US11724765
申请日：2007-03-16
申请人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
发明人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
IPC分类号： G06F13/36
CPC分类号： G06F13/4217
摘要： Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.
摘要翻译：公开了早期固定延迟减法解码的系统和方法。推定或条件地减法解码装置在与正解码的时间段相同的固定时间段内确认总线事务。因此，可以在每个新的时间段内完成新的公交交易的流水线。如果在固定时间段内没有发生确认，则可以重试总线事务。

2. 发明申请

US20060143409A1 Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput 有权
标题翻译：用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置
公开(公告)号：US20060143409A1
公开(公告)日：2006-06-29
申请号：US11027649
申请日：2004-12-29
申请人： Quinn Merrell , R. O'Bleness , Sujat Jamil , Hang Nguyen
发明人： Quinn Merrell , R. O'Bleness , Sujat Jamil , Hang Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating frequency of the cache is higher than the operating frequency of the processor.
摘要翻译：公开了一种用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置。在一个实施例中，装置包括高速缓存，处理器和频率控制器。频率控制器将以高功率模式操作该设备，其中高速缓存的工作频率高于处理器的工作频率。

3. 发明申请

US20060143397A1 Dirty line hint array for cache flushing 审中-公开
标题翻译：用于缓冲区冲洗的脏线提示数组
公开(公告)号：US20060143397A1
公开(公告)日：2006-06-29
申请号：US11027637
申请日：2004-12-29
申请人： R. O'Bleness , Sujat Jamil , Quinn Merrell , Hang Nguyen
发明人： R. O'Bleness , Sujat Jamil , Quinn Merrell , Hang Nguyen
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G06F12/0891
摘要： Techniques for using a dirty line hint array when flushing a cache are disclosed. In one embodiment, an apparatus includes a number of hint bits. Each hint bit corresponds to a number of cache lines, and indicates whether at least one of those cache lines is dirty.
摘要翻译：公开了在刷新缓存时使用脏行提示数组的技术。在一个实施例中，装置包括多个提示位。每个提示位对应于多个高速缓存行，并且指示这些高速缓存行中的至少一个是否是脏的。

4. 发明申请

US20060143358A1 Method and apparatus for implementing heterogeneous interconnects 有权
公开(公告)号：US20060143358A1
公开(公告)日：2006-06-29
申请号：US11027709
申请日：2004-12-28
申请人： Samantha Edirisooriya , Steven Tu , Gregory Tse , Sujat Jamil , David Miner , R. O'Bleness , Hang Nguyen
发明人： Samantha Edirisooriya , Steven Tu , Gregory Tse , Sujat Jamil , David Miner , R. O'Bleness , Hang Nguyen
IPC分类号： G06F13/00
CPC分类号： G06F13/36 , G06F13/4022
摘要： Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

5. 发明申请

US20060004961A1 Direct processor cache access within a system having a coherent multi-processor protocol 失效
公开(公告)号：US20060004961A1
公开(公告)日：2006-01-05
申请号：US10882509
申请日：2004-06-30
申请人： Steven Tu , Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Hang Nguyen
发明人： Steven Tu , Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Hang Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0862 , G06F2212/507
摘要： Methods and apparatuses for pushing data from a system agent to a cache memory.

6. 发明申请

US20060271716A1 Apparatus and method for supporting heterogeneous agents in on-chip busses 有权
标题翻译：在片上总线上支持异构代理的装置和方法
公开(公告)号：US20060271716A1
公开(公告)日：2006-11-30
申请号：US11501572
申请日：2006-08-08
申请人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
发明人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F13/362
摘要： A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.
摘要翻译：一种用于在片上总线上支持异构代理的方法和装置。在一个实施例中，该方法包括在至少第一总线代理和第二总线代理之间检测总线仲裁事件。在一个实施例中，当至少第一总线代理和第二总线代理在单个时钟周期中断言其各自的总线请求信号时，检测总线仲裁事件。一旦检测到总线仲裁事件，当第一总线代理和第二总线代理具有不同的授权 - 有效延迟时，总线所有权可以被授予第一总线代理和第二总线代理两者。在该实施例中，异构总线代理可以在总线上共存而不需要在建立总线所有权之后浪费或未使用的总线周期。描述和要求保护其他实施例。

7. 发明申请

US20050289303A1 Pushing of clean data to one or more processors in a system having a coherency protocol 有权
标题翻译：将干净的数据推送到具有一致性协议的系统中的一个或多个处理器
公开(公告)号：US20050289303A1
公开(公告)日：2005-12-29
申请号：US10881607
申请日：2004-06-29
申请人： Sujat Jamil , Hang Nguyen , Samantha Edirisooriya , David Miner , R. O'Bleness , Steven Tu
发明人： Sujat Jamil , Hang Nguyen , Samantha Edirisooriya , David Miner , R. O'Bleness , Steven Tu
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0833 , G06F12/0835
摘要： Techniques for pushing data to multiple processors in a clean state.
摘要翻译：将数据推送到处于干净状态的多个处理器的技术。

8. 发明申请

US20050193176A1 Cache memory to support a processor's power mode of operation 有权
标题翻译：缓存内存支持处理器的电源运行模式
公开(公告)号：US20050193176A1
公开(公告)日：2005-09-01
申请号：US11124309
申请日：2005-05-06
申请人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu
发明人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/126 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A system, method, and apparatus for a cache memory to support a low power mode of operation.
摘要翻译：一种用于缓存存储器以支持低功率操作模式的系统，方法和装置。

9. 发明申请

US20050216632A1 Apparatus and method for supporting heterogeneous agents in on-chip busses 有权
标题翻译：在片上总线上支持异构代理的装置和方法
公开(公告)号：US20050216632A1
公开(公告)日：2005-09-29
申请号：US10797771
申请日：2004-03-10
申请人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
发明人： Samantha Edirisooriya , Sujat Jamil , David Miner , R. O'Bleness , Steven Tu , Hang Nguyen
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40
CPC分类号： G06F13/4031 , G06F13/362
摘要： A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.
摘要翻译：一种用于在片上总线上支持异构代理的方法和装置。在一个实施例中，该方法包括检测至少第一总线代理和第二总线代理之间的总线仲裁事件。在一个实施例中，当至少第一总线代理和第二总线代理在单个时钟周期中断言其各自的总线请求信号时，检测总线仲裁事件。一旦检测到总线仲裁事件，当第一总线代理和第二总线代理具有不同的授权 - 有效延迟时，总线所有权可以被授予第一总线代理和第二总线代理两者。在该实施例中，异构总线代理可以在总线上共存而不需要在建立总线所有权之后浪费或未使用的总线周期。描述和要求保护其他实施例。

10. 发明申请

US20050166020A1 Methods and apparatus for cache intervention 有权
标题翻译：缓存干预的方法和设备
公开(公告)号：US20050166020A1
公开(公告)日：2005-07-28
申请号：US11084286
申请日：2005-03-18
申请人： Sujat Jamil , Hang Nguyen , Samantha Edirisooriya , David Miner , R. O'Bleness , Steven Tu
发明人： Sujat Jamil , Hang Nguyen , Samantha Edirisooriya , David Miner , R. O'Bleness , Steven Tu
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831 , Y02D10/13
摘要： Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.
摘要翻译：提供了当传送块的状态处于非修改状态和/或修改状态时，缓存到高速缓存块传输（即干预）的方法和装置，而不断言命中修改的信号线。在一个示例中，第一高速缓存在传送之前保存该存储器块。当与第二高速缓存相关联的处理器尝试从主存储器读取块时，无论缓存块的状态（修改或未修改）如何，第一高速缓存都将该块介入并提供给第二高速缓存。此外，与第一缓存相关联的代理断言“命中”信号线，而不管缓存块的状态（修改或未修改）。与第一个高速缓存相关联的代理不会声明“命中修改”的信号线。

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