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1. 发明授权

US08482985B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08482985B2
公开(公告)日：2013-07-09
申请号：US13315516
申请日：2011-12-09
申请人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
发明人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
IPC分类号： G11C16/06
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3409 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.
摘要翻译：根据实施例的非易失性半导体存储装置包括执行擦除序列的擦除电路，其中在擦除序列中，擦除电路执行：在擦除操作之后将选择存储单元组改变为擦除状态的擦除操作，对选择存储单元组进行软编程操作以解决过擦除状态，并且在软编程操作之后，对第一部分选择存储单元组和第二部分选择存储单元组的至少一个部分选择存储单元组执行第一软程序验证操作部分选择存储单元组，以确认部分选择存储单元组是否包括具有等于或大于预定第一阈值的阈值的预定数量的存储单元或更多个，以及在第一软程序验证操作之后。

2. 发明申请

US20120243330A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120243330A1
公开(公告)日：2012-09-27
申请号：US13315516
申请日：2011-12-09
申请人： Ayako YAMANO , Osamu Nagao , Toshiaki Edahiro
发明人： Ayako YAMANO , Osamu Nagao , Toshiaki Edahiro
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3409 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.
摘要翻译：根据实施例的非易失性半导体存储装置包括执行擦除序列的擦除电路，其中在擦除序列中，擦除电路执行：在擦除操作之后将选择存储单元组改变为擦除状态的擦除操作，对选择存储单元组进行软编程操作以解决过擦除状态，并且在软编程操作之后，对第一部分选择存储单元组和第二部分选择存储单元组的至少一个部分选择存储单元组执行第一软程序验证操作部分选择存储单元组，以确认部分选择存储单元组是否包括具有等于或大于预定第一阈值的阈值的预定数量的存储单元或更多个，以及在第一软程序验证操作之后。

3. 发明授权

US09003105B2 Semiconductor memory device and method for writing therein 有权
标题翻译：半导体存储器件及其中写入的方法
公开(公告)号：US09003105B2
公开(公告)日：2015-04-07
申请号：US13603697
申请日：2012-09-05
申请人： Ayako Yamano , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
发明人： Ayako Yamano , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
IPC分类号： G06F12/08 , G06F12/02 , G11C16/00 , G11C11/56 , G11C16/16
CPC分类号： G06F12/0891 , G06F12/0246 , G06F2212/7209 , G11C11/5635 , G11C16/00 , G11C16/16 , Y02D10/13
摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定当第一个标志表示有效时，块是可写的。

4. 发明申请

US20130246730A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR WRITING THEREIN 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20130246730A1
公开(公告)日：2013-09-19
申请号：US13603697
申请日：2012-09-05
申请人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
发明人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0246 , G06F2212/7209 , G11C11/5635 , G11C16/00 , G11C16/16 , Y02D10/13
摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定当第一个标志表示有效时，块是可写的。

5. 发明申请

US20100208519A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME 审中-公开
标题翻译：半导体存储器件及其读取方法
公开(公告)号：US20100208519A1
公开(公告)日：2010-08-19
申请号：US12706306
申请日：2010-02-16
申请人： Hitoshi SHIGA , Osamu Nagao
发明人： Hitoshi SHIGA , Osamu Nagao
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/3404
摘要： First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier.Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for reading data or threshold voltage information among plural values and selecting one of plural data read out by the plural values based on data retained in first data retaining circuit. Third operation of externally outputting selected data is executed simultaneously with one of successive first and second operations.
摘要翻译：第一和第二数据保持电路保持从存储单元读取的数据和指示存储单元的多个阈值电压分布阈值电压位于何处的阈值电压信息。计算装置执行在第一和第二数据保持电路中保留的数据和由读出放大器读取的数据之间的计算。控制电路执行从连接到与选择的存储单元连接的第一字线相邻的第二字线的相邻存储单元读取数据并将数据保存在第一数据保持电路中的第一操作，以及改变施加到第一字线的各字线电压的第二操作用于在多个值之间读取数据或阈值电压信息，并且基于保留在第一数据保持电路中的数据选择由多个值读出的多个数据中的一个。在连续的第一和第二操作之一中同时执行外部输出所选数据的第三操作。

6. 发明授权

US08320187B2 Nonvolatile semiconductor memory and control method thereof 有权
标题翻译：非易失性半导体存储器及其控制方法
公开(公告)号：US08320187B2
公开(公告)日：2012-11-27
申请号：US13234628
申请日：2011-09-16
申请人： Osamu Nagao
发明人： Osamu Nagao
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5607 , G11C11/5614 , G11C11/5642 , G11C11/5664 , G11C11/5671 , G11C11/5678 , G11C11/5685 , G11C16/0483 , G11C16/3459 , G11C2211/5621
摘要： According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison.
摘要翻译：根据一个实施例，非易失性半导体存储器包括存储多电平数据的存储单元，扫描待写入存储器单元的数量的位扫描电路和通过验证的存储单元的数量;处理单元基于比特扫描电路的扫描结果执行操作处理，以及控制电路，用于根据第一模式控制写入数据的操作，其中在较低数据期间计算用于上位数据写入的电压写入和第二模式使用基于设置信息的电压。位扫描电路在开始写入之前扫描要写入的存储器单元的数量，并且处理单元将待写入的存储器单元的数量与标准进行比较，并且基于用于写入的第一和第二模式之一确定基于比较的结果。

7. 发明授权

US07382651B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07382651B2
公开(公告)日：2008-06-03
申请号：US11616122
申请日：2006-12-26
申请人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
发明人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/0483
摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.
摘要翻译：在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管成为一个离开的国家。接下来，向阱区域提供高电压，并且擦除所选块的数据。然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

8. 发明申请

US20070147117A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070147117A1
公开(公告)日：2007-06-28
申请号：US11616122
申请日：2006-12-26
申请人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
发明人： Osamu Nagao , Yasuyuki Fukuda , Hideo Mukai
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0483
摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.
摘要翻译：在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管成为一个离开的国家。接下来，向阱区域提供高电压，并且擦除所选块的数据。然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

9. 发明授权

US08339866B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08339866B2
公开(公告)日：2012-12-25
申请号：US12570259
申请日：2009-09-30
申请人： Akihiro Imamoto , Osamu Nagao
发明人： Akihiro Imamoto , Osamu Nagao
IPC分类号： G11C16/14 , G11C16/16 , G11C16/06 , G11C16/04 , G11C16/10 , G11C16/34 , G11C16/08
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344 , G11C16/3445
摘要： A NAND type flash memory for erasing data every block including plural memory cell transistors that are provided every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating gates, data in the memory cell transistors being rewritable by controlling charge amounts accumulated in the floating gates, and a row decoder having a plurality of MOS transistors having drains that are respectively connected to corresponding word lines connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate and source voltages of the MOS transistors.
摘要翻译：一种NAND型闪速存储器，用于每块包括多个存储单元晶体管的每个块擦除数据，并且具有通过在半导体衬底中形成的阱上方的第一栅极绝缘膜形成的浮动栅极，以及通过第二栅极绝缘膜形成的控制栅极，门，存储单元晶体管中的数据可通过控制浮置栅极中累积的电荷量而被重写，以及具有多个MOS晶体管的行解码器，其具有分别连接到连接到多个存储器的控制栅极的相应字线的漏极单元晶体管，行解码器控制MOS晶体管的栅极和源极电压。

10. 发明申请

US20130070546A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130070546A1
公开(公告)日：2013-03-21
申请号：US13423759
申请日：2012-03-19
申请人： Osamu Nagao , Hitoshi Shiga
发明人： Osamu Nagao , Hitoshi Shiga
IPC分类号： G11C29/44
CPC分类号： G11C16/08 , G11C16/0483 , G11C29/04 , G11C29/82 , G11C2029/4402
摘要： A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural blocks arranged in a first direction, each block containing plural memory cells operative to store data; a row decoder including a faulty block information holder circuit operative to store faulty block information indicative that the block is a faulty block; and a faulty block detector circuit operative to, when each of block groups includes at least one of the plural blocks, subject one of the block groups to a first detection step of simultaneously and intensively referring to pieces of faulty block information respectively corresponding to the plural blocks in one of the block groups simultaneously to detect whether the block group contains a faulty block.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括沿第一方向布置的多个块，每个块包含可操作以存储数据的多个存储单元; 行解码器，其包括故障块信息保持器电路，用于存储指示所述块是故障块的故障块信息; 以及故障块检测器电路，其操作用于当每个块组包括所述多个块中的至少一个时，将所述块组中的一个对象到第一检测步骤，同时且集中地参考分别对应于所述多个块的故障块信息块中的块之一同时检测块组是否包含故障块。

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