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1. 发明申请

US20130246730A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR WRITING THEREIN 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20130246730A1
公开(公告)日：2013-09-19
申请号：US13603697
申请日：2012-09-05
申请人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
发明人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0246 , G06F2212/7209 , G11C11/5635 , G11C16/00 , G11C16/16 , Y02D10/13
摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定当第一个标志表示有效时，块是可写的。

2. 发明授权

US09003105B2 Semiconductor memory device and method for writing therein 有权
标题翻译：半导体存储器件及其中写入的方法
公开(公告)号：US09003105B2
公开(公告)日：2015-04-07
申请号：US13603697
申请日：2012-09-05
申请人： Ayako Yamano , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
发明人： Ayako Yamano , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
IPC分类号： G06F12/08 , G06F12/02 , G11C16/00 , G11C11/56 , G11C16/16
CPC分类号： G06F12/0891 , G06F12/0246 , G06F2212/7209 , G11C11/5635 , G11C16/00 , G11C16/16 , Y02D10/13
摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定当第一个标志表示有效时，块是可写的。

3. 发明申请

US20100241794A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100241794A1
公开(公告)日：2010-09-23
申请号：US12725519
申请日：2010-03-17
申请人： Osamu NAGAO , Hitoshi Shiga
发明人： Osamu NAGAO , Hitoshi Shiga
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7209
摘要： A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.
摘要翻译：根据本发明的一个方面的非易失性半导体存储器件包括：设置为以页为单位执行编程的存储单元阵列; 以及设置用于控制编程的控制电路。控制电路包括：对存储单元进行第一检测的装置，该存储单元在作为小于页面的单位提供的部分中，同时对要写入页面的存储单元进行编程; 并且意味着当第一检测中检测到的部分中未写入状态的存储单元的数目等于或等于或等于或小于第二检测时，考虑到冗余区域引起的故障缓解，并且当页面中未写入状态的存储单元的数量等于或小于第二常数时，结束程序操作。

4. 发明申请

US20130070546A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130070546A1
公开(公告)日：2013-03-21
申请号：US13423759
申请日：2012-03-19
申请人： Osamu Nagao , Hitoshi Shiga
发明人： Osamu Nagao , Hitoshi Shiga
IPC分类号： G11C29/44
CPC分类号： G11C16/08 , G11C16/0483 , G11C29/04 , G11C29/82 , G11C2029/4402
摘要： A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural blocks arranged in a first direction, each block containing plural memory cells operative to store data; a row decoder including a faulty block information holder circuit operative to store faulty block information indicative that the block is a faulty block; and a faulty block detector circuit operative to, when each of block groups includes at least one of the plural blocks, subject one of the block groups to a first detection step of simultaneously and intensively referring to pieces of faulty block information respectively corresponding to the plural blocks in one of the block groups simultaneously to detect whether the block group contains a faulty block.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括沿第一方向布置的多个块，每个块包含可操作以存储数据的多个存储单元; 行解码器，其包括故障块信息保持器电路，用于存储指示所述块是故障块的故障块信息; 以及故障块检测器电路，其操作用于当每个块组包括所述多个块中的至少一个时，将所述块组中的一个对象到第一检测步骤，同时且集中地参考分别对应于所述多个块的故障块信息块中的块之一同时检测块组是否包含故障块。

5. 发明授权

US08205039B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08205039B2
公开(公告)日：2012-06-19
申请号：US12725519
申请日：2010-03-17
申请人： Osamu Nagao , Hitoshi Shiga
发明人： Osamu Nagao , Hitoshi Shiga
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7209
摘要： A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.
摘要翻译：根据本发明的一个方面的非易失性半导体存储器件包括：设置为以页为单位执行编程的存储单元阵列; 以及设置用于控制编程的控制电路。控制电路包括：对存储单元进行第一检测的装置，该存储单元在作为小于页面的单位提供的部分中，同时对要写入页面的存储单元进行编程; 并且意味着当第一检测中检测到的部分中未写入状态的存储单元的数目等于或等于或等于或小于第二检测时，考虑到冗余区域引起的故障缓解，并且当页面中未写入状态的存储单元的数量等于或小于第二常数时，结束程序操作。

6. 发明授权

US09043679B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09043679B2
公开(公告)日：2015-05-26
申请号：US13719479
申请日：2012-12-19
申请人： Hitoshi Shiga , Hidetaka Tsuji
发明人： Hitoshi Shiga , Hidetaka Tsuji
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1008 , G06F11/1072 , G11C2029/0411
摘要： A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.
摘要翻译：存储器件包括存储数据的存储器芯片和控制存储器芯片的外部控制器。存储器芯片包括被配置为存储两个或多个位的数据的多个存储器单元; 以及内部控制器，其执行包括下页和上页程序操作的页面数据的编程操作，并且对包括下页和上页读操作的页数据执行读操作。外部控制器包括纠错单元，对要编程到存储单元阵列中的数据进行纠错编码，并对数据执行纠错解码。在上层读取操作中，内部控制器将读取页数据从存储单元阵列输出到外部控制器，而不管高层编程操作是否完成。

7. 发明授权

US07978512B2 Semiconductor memory system 有权
标题翻译：半导体存储器系统
公开(公告)号：US07978512B2
公开(公告)日：2011-07-12
申请号：US12557898
申请日：2009-09-11
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C29/00 , G11C2211/5641 , H01L27/11521
摘要： A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.
摘要翻译：半导体存储器系统包括：存储单元阵列，其中布置有多个存储器单元，所述多个存储单元能够在每个存储单元中存储N位信息（其中N是大于3的自然数，除了功率的两个）; 控制电路，被配置为控制对所述存储单元阵列的读，写和擦除操作; 以及ECC电路，被配置为基于冗余数据校正从存储单元阵列读取的数据。共享字线之一并且可以一次写入或读取的存储单元被配置为在其中存储多页数据。存储在多页中的数据的总量被设置为两位数，并且冗余数据被存储在多页的剩余部分中。

8. 发明授权

US07843724B2 Nonvolatile semiconductor memory and data reading method 失效
标题翻译：非易失性半导体存储器和数据读取方法
公开(公告)号：US07843724B2
公开(公告)日：2010-11-30
申请号：US11863915
申请日：2007-09-28
申请人： Hitoshi Shiga , Susumu Fujimura , Yoshihiko Shindo
发明人： Hitoshi Shiga , Susumu Fujimura , Yoshihiko Shindo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要： A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming cortrol section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for deterraining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.
摘要翻译：一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。数据读取和编程cortrol部分包括：相邻的存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据来确定在第一存储器单元中编程4值数据的哪个数据。

9. 发明授权

US07522452B2 Non-volatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07522452B2
公开(公告)日：2009-04-21
申请号：US11769383
申请日：2007-06-27
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C29/88 , G11C2211/5621 , G11C2211/5646
摘要： A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.
摘要翻译：存储单元阵列包括能够存储多值数据的多个存储单元。位线控制电路包括连接到位线的数据存储电路，并且每个存储包括在多值数据中的多组页数据中的一个，位线控制电路控制施加到位的位线电压线。字线控制电路控制施加到字线的字线电压。控制电路控制字线控制电路和位线控制电路。控制电路执行这样的模式，为了区分故障块，可以写入故障块中的全部或特定存储单元，使得故障块中的全部或特定存储单元的阈值电压高于施加的字线电压当读取页面数据集合的第一页数据时，到所选择的字线。

10. 发明申请

US20060227624A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060227624A1
公开(公告)日：2006-10-12
申请号：US11167301
申请日：2005-06-28
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C2207/2245 , G11C2211/5646
摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.
摘要翻译：半导体存储器件包括：存储单元阵列，其中电可重写和非易失性存储器单元被布置为存储多值数据; 读出放大器电路，被配置为读取存储单元阵列中的数据并写入数据; 以及控制器，其被配置为控制所述存储单元阵列的数据读取和写入，其中所述控制器具有如下功能：当上页数据写入序列以故障结束时，所述上页数据为要写入所述存储单元阵列的区域中的一个存储单元阵列，其中已经写入较低页数据，以缓存从存储单元阵列读出并保持在读出放大器电路中的下部页数据。

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