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1. 发明授权

US06549063B1 Evaluation circuit for an anti-fuse 有权
标题翻译：防熔断器评估电路
公开(公告)号：US06549063B1
公开(公告)日：2003-04-15
申请号：US10044470
申请日：2002-01-11
申请人： Gunther Lehmann , Ulrich Frey
发明人： Gunther Lehmann , Ulrich Frey
IPC分类号： H01H3776
CPC分类号： H01L23/5256 , G01R31/07 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged with a predetermined voltage and/or current and the anti-fuse is subsequently evaluated. In one embodiment a precharge voltage sufficient to turn ON a transistor is provided to the gate. Here, an intact (unblown) transistor remains ON over a period of time and a damaged (blown) transistor dissipates the charge voltage and turns OFF. The status of the transistor is subsequently determined by evaluating the resistance between the drain and source. A high resistance indicates a blown condition and a low resistance indicates an unblown condition. In another embodiment, a small current is provided to the gate in which the small current is greater than a leakage current for an intact transistor and is less than a leakage current for a damaged transistor. An intact transistor charges to an ON state over a period of time but a damaged transistor does not because it's leakage current is greater than the small current provided to the gate. Again, the status of the transistor anti-fuse is subsequently determined by evaluating the resistance between the drain and source.
摘要翻译：本发明提供了一种可编程反熔丝元件的评估。对于可编程晶体管反熔丝，反熔丝的栅极以预定的电压和/或电流进行预充电，并且随后评估反熔丝。在一个实施例中，向栅极提供足以导通晶体管的预充电电压。这里，一个完整的（未吹制的）晶体管在一段时间内保持导通，并且损坏的（熔断）晶体管消耗充电电压并且关断。随后通过评估漏极和源极之间的电阻来确定晶体管的状态。高电阻表示吹出状态，低电阻表示未吹出状态。在另一个实施例中，小电流被提供给栅极，其中小电流大于完整晶体管的漏电流，并且小于损坏晶体管的漏电流。完整的晶体管在一段时间内充电到ON状态，但损坏的晶体管不是因为其漏电流大于提供给栅极的小电流。再次，晶体管反熔丝的状态随后通过评估漏极和源极之间的电阻来确定。

2. 发明授权

US06642602B2 Self-terminating blow process of electrical anti-fuses 有权
标题翻译：电气自保险的自终止吹风过程
公开(公告)号：US06642602B2
公开(公告)日：2003-11-04
申请号：US10017036
申请日：2001-12-14
申请人： Gunther Lehmann , Ulrich Frey , Oliver Weinfurtner
发明人： Gunther Lehmann , Ulrich Frey , Oliver Weinfurtner
IPC分类号： H01L2900
CPC分类号： G11C17/18
摘要： An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an “on” signal to the gate (38) of control transistor (36) only when a_“select_” signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.
摘要翻译：由多个由一对导体（16,18）跨过电压源（10）连接的反熔丝电路（24,26,28，N）组成的反熔丝系统。每个反熔丝电路包括与吹扫或控制晶体管（36）串联连接的反熔丝（30）和用于监视反熔丝（30）的状态的控制电路（44），控制电路（44）只有当控制电路（44）的输入端（46）接收到a_“select_”信号，并且如果反熔丝（30）没有被接收，则仅向控制晶体管（36）的栅极（38）提供“接通”信号被吹了在防熔丝（30）熔断之后，控制电路（44）关闭控制晶体管（36），从而在每个反熔丝电路（24,26,28，N）上提供恒定的电源电压，而不管数量如何平行的保险丝已被吹制。

3. 发明授权

US07145216B2 Antifuse programming with relaxed upper current limit 有权
标题翻译：具有放电上限限制的防污编程
公开(公告)号：US07145216B2
公开(公告)日：2006-12-05
申请号：US10361989
申请日：2003-02-11
申请人： Ulrich Frey , Gunther Lehmann
发明人： Ulrich Frey , Gunther Lehmann
IPC分类号： H01L29/00
CPC分类号： G11C17/16
摘要： An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse, and the other current path can be used to detect the status (programmed or not programmed) of the antifuse.
摘要翻译：反熔丝设备包括连接到反熔丝的第一和第二独立电流路径。可以使用其中一条路径来编程反熔丝，另一条电流路径可用于检测反熔丝的状态（已编程或未编程）。

4. 发明授权

US08143694B2 Fuse device 有权
标题翻译：保险丝装置
公开(公告)号：US08143694B2
公开(公告)日：2012-03-27
申请号：US12131134
申请日：2008-06-02
申请人： Vianney Choserot , Gunther Lehmann , Franz Ungar
发明人： Vianney Choserot , Gunther Lehmann , Franz Ungar
IPC分类号： H01L23/52
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.
摘要翻译：本文提供了与保险丝装置，包括熔丝装置的集成电路，实现熔丝装置的方法和编程熔丝装置的方法相关的实施方式。

5. 发明授权

US07633787B2 ROM memory component featuring reduced leakage current, and method for writing the same 有权
标题翻译：具有减少漏电流的ROM存储器组件及其写入方法
公开(公告)号：US07633787B2
公开(公告)日：2009-12-15
申请号：US11661582
申请日：2005-08-18
申请人： Siddarth Gupta , Jean-Yves Larguier , Gunther Lehmann , Yannick Martelloni
发明人： Siddarth Gupta , Jean-Yves Larguier , Gunther Lehmann , Yannick Martelloni
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C2207/2227
摘要： The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.
摘要翻译：本发明涉及一种ROM存储单元，包括连接到字线的第一端子，包括第二端子并包括第三端子，第二端子连接到位线和/或第三端子连接到电源线预充电第三个终端。根据本发明的ROM存储器单元的特征在于，在待机操作模式中，相同的参考电位在每种情况下都应用于第一端子，第二端子和/或第三端子。本发明还涉及一种包括这种ROM存储器单元的ROM存储器组件，以及一种用于从ROM存储单元读取的方法。

6. 发明授权

US07403432B2 Differential read-out circuit for fuse memory cells 有权
标题翻译：保险丝存储器单元的差分读出电路
公开(公告)号：US07403432B2
公开(公告)日：2008-07-22
申请号：US11358374
申请日：2006-02-21
申请人： Gunther Lehmann , Vianney Choserot , Jean-Yves Larguier
发明人： Gunther Lehmann , Vianney Choserot , Jean-Yves Larguier
IPC分类号： G11C7/10
CPC分类号： G11C7/062 , G11C17/18
摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.
摘要翻译：公开了一种读出电路，其中电路从包括两个非易失性存储器单元的存储器单元中读出信息。单元具有不同的编程状态，并且存储器单元的存储器信息由两个存储器单元的编程状态给出。读出电路具有易失性信号存储器，其输入连接到存储器单元的读取输出。

7. 发明申请

US20070121400A1 Supplying voltage to a bit line of a memory device 有权
标题翻译：向存储器件的位线提供电压
公开(公告)号：US20070121400A1
公开(公告)日：2007-05-31
申请号：US11528079
申请日：2006-09-26
申请人： Gunther Lehmann , Yannick Martelloni , Devesh Dwivedi , Siddharth Gupta
发明人： Gunther Lehmann , Yannick Martelloni , Devesh Dwivedi , Siddharth Gupta
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C17/12
摘要： A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.
摘要翻译：一种方法向存储器件的位线提供电压。该方法包括使用预充电装置将位线预充电到输出电位，在与位线有关的读取动作期间停用预充电装置，在读取动作期间通过位线读取信息，以及在路线期间进行路由读取动作，将虚拟电压提供到存储器件的电源电位，以将电压提供给分配给位线的存储器件的存储器单元。作为虚拟电压供给线的电位的函数，位线的预充电装置被激活/去激活。

8. 发明申请

US20060203585A1 Differential read-out circuit for fuse memory cells 有权
标题翻译：保险丝存储器单元的差分读出电路
公开(公告)号：US20060203585A1
公开(公告)日：2006-09-14
申请号：US11358374
申请日：2006-02-21
申请人： Gunther Lehmann , Vianney Choserot , Jean-Yves Larguier
发明人： Gunther Lehmann , Vianney Choserot , Jean-Yves Larguier
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C17/18
摘要： A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells (F2, F3). The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells (F2, F3). The read-out circuit has a volatile signal memory (INV4, INV5), the inputs of which are connected to the read outputs of the memory cells (F2, F3).
摘要翻译：公开了一种读出电路，其中电路从包括两个非易失性存储单元（F 2，F 3）的存储单元中读出信息。单元具有不同的编程状态，存储单元的存储器信息由两个存储单元（F 2，F 3）的编程状态给出。读出电路具有易失性信号存储器（INV 4，INV 5），其输入端连接到存储单元（F 2，F 3）的读出端。

9. 发明授权

US06603694B1 Dynamic memory refresh circuitry 有权
标题翻译：动态内存刷新电路
公开(公告)号：US06603694B1
公开(公告)日：2003-08-05
申请号：US10068789
申请日：2002-02-05
申请人： Gerd Frankowsky , Gunther Lehmann
发明人： Gerd Frankowsky , Gunther Lehmann
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for determining data retention times in each one of the memory cells and from such determination refresh address modification signals. Also provided is a refresh address generator formed on the chip and fed by refresh command signals generated externally of the chip and by the address modification signals. The refresh address generator supplies an internal refresh commands along with refresh addresses to the array of memory cells. The cells have data stored therein refreshed in response to such internal refresh commands. The refresh rate analysis circuit determines cells in the array having data retention times less than a predetermined value.
摘要翻译：提供了用于刷新存储在动态存储单元阵列中的数据的电路。该电路包括集成电路芯片。芯片具有形成在其上的存储单元阵列。该电路还包括用于确定每个存储器单元中的数据保持时间的刷新率分析电路，以及这些确定刷新地址修改信号。还提供了一种刷新地址生成器，其形成在芯片上并由芯片外部产生的刷新命令信号和地址修改信号馈送。刷新地址生成器向内存单元阵列提供内部刷新命令以及刷新地址。小区具有响应于这种内部刷新命令刷新的数据。刷新率分析电路确定具有小于预定值的数据保留时间的阵列中的单元。

10. 发明授权

US06404019B1 Sense amplifier 失效
标题翻译：感应放大器
公开(公告)号：US06404019B1
公开(公告)日：2002-06-11
申请号：US09676870
申请日：2000-09-29
申请人： Armin M. Reith , Tina Leidinger , Gunther Lehmann
发明人： Armin M. Reith , Tina Leidinger , Gunther Lehmann
IPC分类号： H01L2994
CPC分类号： G11C7/065 , H01L27/10897
摘要： A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.
摘要翻译：在硅集成电路中形成用于动态随机存取存储器的读出放大器。这种读出放大器的阵列的间距等于存储器阵列的位线对的间距。每个读出放大器阵列由具有U形栅电极的给定n或p沟道型金属氧化物半导体（MOS）晶体管的四行晶体管形成。读出放大器的每行晶体管中的晶体管的栅电极以预先选定的量偏离前一行。通过读出放大器的位线是直的，没有偏移影响光刻性能，也没有突起增加位线的电容。这种读出放大器阵列的尺寸等于位线对的最小尺寸，因此不会导致存储器单元阵列的宽度的任何增加。

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