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1. 发明授权

US08871025B2 SiC single crystals with reduced dislocation density grown by step-wise periodic perturbation technique 有权
标题翻译：通过逐步周期扰动技术生长的具有降低的位错密度的SiC单晶
公开(公告)号：US08871025B2
公开(公告)日：2014-10-28
申请号：US12441583
申请日：2007-09-27
申请人： Avinash Gupta , Utpal K. Chakrabarti , Jihong Chen , Edward Semenas , Ping Wu
发明人： Avinash Gupta , Utpal K. Chakrabarti , Jihong Chen , Edward Semenas , Ping Wu
IPC分类号： C30B28/14 , C30B29/36 , C30B23/00
CPC分类号： C30B29/36 , C30B23/002 , C30B23/005
摘要： In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.
摘要翻译：在晶体生长方法中，种子晶体8和源材料4以生长坩埚6内的间隔关系设置。然后在其中建立用于在生长坩埚6中生长晶体14的起始条件。起始条件包括：生长坩埚6内的合适气体，生长坩埚6内部的气体的适当压力，以及生长坩埚6中适当的温度，其使得源材料4升华并经由温度梯度在生长坩埚6中，升华的源材料析出的晶种8。在生长坩埚6内生长晶体14期间，生长坩埚6内的至少一个以下生长条件间歇性地变化：生长坩埚6中的气体，生长坩埚中的气体压力 6，以及生长坩埚6中的温度。

2. 发明申请

US20100031877A1 SIC SINGLE CRYSTALS WITH REDUCED DISLOCATION DENSITY GROWN BY STEP-WISE PERIODIC PERTURBATION TECHNIQUE 有权
标题翻译： SIC单晶体具有降低的偏心密度，由步进周期性刺激技术
公开(公告)号：US20100031877A1
公开(公告)日：2010-02-11
申请号：US12441583
申请日：2007-09-27
申请人： Avinash Gupta , Utpal K. Chakrabarti , Jihong Chen , Edward Semenas , Ping Wu
发明人： Avinash Gupta , Utpal K. Chakrabarti , Jihong Chen , Edward Semenas , Ping Wu
IPC分类号： C30B23/02
CPC分类号： C30B29/36 , C30B23/002 , C30B23/005
摘要： In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.
摘要翻译：在晶体生长方法中，种子晶体8和源材料4以生长坩埚6内的间隔关系设置。然后在其中建立用于在生长坩埚6中生长晶体14的起始条件。起始条件包括：生长坩埚6内的合适气体，生长坩埚6内部的气体的适当压力，以及生长坩埚6中适当的温度，其使得源材料4升华并经由温度梯度在生长坩埚6中，升华的源材料析出的晶种8。在生长坩埚6内生长晶体14期间，生长坩埚6内的至少一个以下生长条件间歇性地变化：生长坩埚6中的气体，生长坩埚中的气体压力 6，以及生长坩埚6中的温度。

3. 发明授权

US07767022B1 Method of annealing a sublimation grown crystal 有权
标题翻译：使升华生长的晶体退火的方法
公开(公告)号：US07767022B1
公开(公告)日：2010-08-03
申请号：US11788384
申请日：2007-04-19
申请人： Avinash K. Gupta , Ilya Zwieback , Jihong Chen , Marcus Getkin , Walter R. M. Stepko , Edward Semenas
发明人： Avinash K. Gupta , Ilya Zwieback , Jihong Chen , Marcus Getkin , Walter R. M. Stepko , Edward Semenas
IPC分类号： C30B23/00
CPC分类号： C30B29/36 , C30B23/00 , C30B33/02
摘要： A crystal is sublimation grown in a crucible by way of a temperature gradient in the presence of between 1 and 200 Torr of inert gas. The pressure of the inert gas is then increased to between 300 and 600 Torr, while the temperature gradient is maintained substantially constant. The temperature gradient is then reduced and the temperature in the crucible is increased sufficiently to anneal the crystal. Following cooling and removal from the crucible, the crystal is heated in the presence of oxygen in an enclosure to a temperature sufficient to remove unwanted material from the crystal. Following cooling and removal from the enclosure, the crystal surrounded by another instance of the source material is heated in a crucible in the presence 200 and 600 Torr of inert gas to a temperature sufficient to anneal the crystal.
摘要翻译：在惰性气体的1至200乇的存在下，通过温度梯度在坩埚中生长晶体。然后将惰性气体的压力增加到300至600托之间，同时温度梯度保持基本恒定。然后降低温度梯度，并使坩埚中的温度充分增加以使晶体退火。在从坩埚中冷却和除去之后，将晶体在外壳中的氧气存在下加热到足以从晶体去除不需要的材料的温度。在从壳体冷却和除去之后，将源材料的另一个实例包围的晶体在惰性气体存在的200和600乇的坩埚中加热到足以使晶体退火的温度。

4. 发明申请

US20080190355A1 Low-Doped Semi-Insulating Sic Crystals and Method 审中-公开
标题翻译：低掺杂半绝缘矽晶体和方法
公开(公告)号：US20080190355A1
公开(公告)日：2008-08-14
申请号：US11629584
申请日：2005-07-06
申请人： Jihong Chen , Ilya Zwieback , Avinash K. Gupta , Donovan L. Barrett , Richard H. Hopkins , Edward Semenas , Thomas A. Anderson , Andrew E. Souzis
发明人： Jihong Chen , Ilya Zwieback , Avinash K. Gupta , Donovan L. Barrett , Richard H. Hopkins , Edward Semenas , Thomas A. Anderson , Andrew E. Souzis
IPC分类号： C30B33/02 , H01B1/02
CPC分类号： H01L29/1608 , C30B23/00 , C30B29/36 , H01L21/02378 , H01L21/02529 , H01L21/02581 , H01L21/02631
摘要： The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm−3, and preferably to below 1·1016 cm−3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors. The deep level impurity comprises one of selected metals from the periodic groups IB, IIB, IIIB, IVB, VB, VIB, VIIB and VIIIB. Vanadium is a preferred deep level element. In addition to controlling the resistivity and capacitance, a further advantage of the invention is an increase in electrical uniformity over the entire crystal and reduction in the density of crystal defects.
摘要翻译：本发明涉及用于半导体器件的半绝缘碳化硅的衬底及其制造方法。基板的电阻率高于106欧姆 - 厘米，优选高于108欧姆 - 厘米，最优选高于109欧姆 - 厘米，电容低于5 pF / mm2，最好低于1 pF / mm2。基板的电学特性由少量的加入的深度杂质控制，其浓度足够大以控制电气行为，但足够小以避免结构缺陷。底物具有无意的背景杂质浓度，包括浅供体和受体，故意降低至5.1016cm-3以下，优选低于1.1016cm-3，深层杂质的浓度较高，优选至少高两倍，比浅受体和浅供体的浓度之间的差异。深层杂质包括选自周期性基团IB，IIB，IIIB，IVB，VB，VIB，VIIB和VIIIB的金属之一。钒是首选的深层元素。除了控制电阻率和电容之外，本发明的另一个优点是在整个晶体上的电均匀性的增加和晶体缺陷密度的降低。

5. 发明申请

US20130193559A1 CAST SILICON ingot prepared BY DIRECTIONAL SOLIDIFICATION 审中-公开
标题翻译： CAST硅胶锭由方向固化制备
公开(公告)号：US20130193559A1
公开(公告)日：2013-08-01
申请号：US13360144
申请日：2012-01-27
申请人： Jihong Chen
发明人： Jihong Chen
IPC分类号： H01L29/30
CPC分类号： H01L31/028 , C30B11/002 , C30B11/14 , H01L31/03682 , H01L31/182 , Y02E10/546 , Y02E10/547 , Y02P70/521
摘要： A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.
摘要翻译：铸造硅晶锭包括两个主要的大致平行的表面，其中一个是前表面，另一个是后表面; 连接前表面和后表面的周边表面; 以及前表面和后表面之间的主体区域; 其中所述铸造硅晶锭的横向尺寸不小于约5厘米; 铸硅晶锭的位错密度小于1000位错/ cm2。从铸硅晶锭切片的晶片具有至少17.5％的太阳能电池效率和光诱导的降解不大于0.2％。

6. 发明授权

US07371648B2 Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same 有权
标题翻译：具有改善的击穿电压的晶体管器件的制造方法和使用其的集成电路的制造方法
公开(公告)号：US07371648B2
公开(公告)日：2008-05-13
申请号：US11469512
申请日：2006-09-01
申请人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
发明人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
IPC分类号： H01L21/336 , H01L21/04 , H01L21/425
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.
摘要翻译：本发明提供一种晶体管器件的制造方法及其制造方法。制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

7. 发明申请

US20080057654A1 METHOD FOR MANUFACTURING A TRANSISTOR DEVICE HAVING AN IMPROVED BREAKDOWN VOLTAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT USING THE SAME 有权
标题翻译：具有改进的断开电压的晶体管器件的制造方法和使用其制造集成电路的方法
公开(公告)号：US20080057654A1
公开(公告)日：2008-03-06
申请号：US11469512
申请日：2006-09-01
申请人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
发明人： Jihong Chen , Srinivasan Chakravarthi , Eddie H. Breashears , Amitabh Jain
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.
摘要翻译：本发明提供一种晶体管器件的制造方法及其制造方法。制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

8. 发明申请

US20130192516A1 METHOD OF PREPARING CAST SILICON BY DIRECTIONAL SOLIDIFICATION 审中-公开
标题翻译：通过定向固化法制备硅酸钠的方法
公开(公告)号：US20130192516A1
公开(公告)日：2013-08-01
申请号：US13360116
申请日：2012-01-27
申请人： Jihong Chen , Aditya Deshpande
发明人： Jihong Chen , Aditya Deshpande
IPC分类号： C30B19/08
CPC分类号： C30B11/002 , C30B11/14 , C30B29/06
摘要： A method of preparing a silicon melt in a crucible for use in the manufacture of cast silicon, wherein the crucible comprises an opening, an opposing bottom surface, and at least one sidewall joining the opening and the bottom surface. The method comprises charging a silicon spacer to the bottom surface of the crucible; arranging a monocrystalline silicon seed crystal on the silicon spacer such that no surface of the monocrystalline silicon material is in contact with the bottom surface of the crucible; charging polycrystalline silicon feedstock to the crucible; and applying heat through at least one of the opening and the at least one sidewall in order to form a partially melted charge of silicon in the crucible.
摘要翻译：一种在用于制造铸硅的坩埚中制备硅熔体的方法，其中坩埚包括开口，相对的底表面和连接开口和底表面的至少一个侧壁。该方法包括将硅隔离物装入坩埚的底表面; 在硅间隔物上布置单晶硅晶种，使得单晶硅材料的表面不与坩埚的底表面接触; 将多晶硅原料装入坩埚中; 并且通过所述开口和所述至少一个侧壁中的至少一个来施加热量，以便在所述坩埚中形成部分熔融的硅填充物。

9. 发明申请

US20050212041A1 Novel process method of source drain spacer engineering to improve transistor capacitance 审中-公开
标题翻译：源极间隔工程的新型工艺方法，以提高晶体管电容
公开(公告)号：US20050212041A1
公开(公告)日：2005-09-29
申请号：US11127941
申请日：2005-05-11
申请人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
发明人： Zhiqiang Wu , Jihong Chen , Kaiping Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/76
CPC分类号： H01L21/2652 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66598 , H01L29/7833
摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.
摘要翻译：提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。补偿区域比源极和漏极区域稍微间隔开。该间隔影响电位轮廓并降低晶体管内的结电容。通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

10. 发明授权

US07691714B2 Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor 有权
标题翻译：具有位于由源/漏区产生的边界内的位错环的半导体器件及其制造方法
公开(公告)号：US07691714B2
公开(公告)日：2010-04-06
申请号：US11042415
申请日：2005-01-25
申请人： Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
发明人： Antonio Luis Pacheco Rotondaro , Kaiping Liu , Jihong Chen , Amitabh Jain
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823871
摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
摘要翻译：本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界。该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

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