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1. 发明授权

US5341049A Integrated circuit having alternate rows of logic cells and I/O cells 失效
标题翻译：集成电路具有交替行的逻辑单元和I / O单元
公开(公告)号：US5341049A
公开(公告)日：1994-08-23
申请号：US916430
申请日：1992-07-21
申请人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
发明人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735 , H01L27/118 , H01L2224/11
摘要： A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.
摘要翻译：半导体IC器件具有与形成在大致矩形形状的半导体衬底的主表面中的输入/输出电路连接的输入/输出电路和内部逻辑电路。输入/输出电路被划分为至少两个输入/输出电路块，使得由基板的主表面上的划分限定的逻辑电路块的边缘沿着与一对相对侧基本平行的方向延伸的基底。内部逻辑电路被分成至少三个逻辑电路块，使得由衬底的主表面上的划分限定的逻辑电路块的边缘沿上述方向延伸。每个输入/输出电路块被夹在相邻布置的两个逻辑电路块中并与其电连接。

2. 发明授权

US5898636A Semiconductor integrated circuit device with interleaved memory and logic blocks 失效
标题翻译：具有交错存储器和逻辑块的半导体集成电路器件
公开(公告)号：US5898636A
公开(公告)日：1999-04-27
申请号：US255240
申请日：1994-06-07
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177 , H01L21/82
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.
摘要翻译：一种半导体集成电路器件，具有存储部分和形成有相同半导体衬底的逻辑电路部分，该半导体衬底包括第一逻辑电路块，布置在与设置第一逻辑电路块的区域不同的区域中的第二逻辑电路块，以及相对设置的一对存储器块，使得第二逻辑电路块在其间。存储在一对存储器块中的数据被发送到第二逻辑电路块，用于经由设置在第二逻辑电路块上的存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。

3. 发明授权

US6034912A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US6034912A
公开(公告)日：2000-03-07
申请号：US145076
申请日：1998-09-01
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.
摘要翻译：半导体器件的存储部分和逻辑电路部分形成在单个半导体衬底上，其中第一逻辑电路块和第二逻辑电路块形成在不同的区域中，并且第二逻辑电路位于一对存储块之间。存储在一对存储器块中的数据被发送到第二逻辑电路块，以经由存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。输入到半导体芯片的中心部分的时钟信号被提供给从中心部分等距设置的多个第一状态时钟分配电路，然后被提供给至少等距地从第一状态中的每个状态设置的多个第二级时钟分配电路时钟分配电路。接下来，时钟信号被提供给从每个第二级时钟分配电路等距离设置的多个第三状态时钟分配电路，然后提供给从每个第三级时钟分配电路等距设置的多个最后级时钟分配电路。从这些最终级时钟分配电路，将时钟信号提供给其单位内的内部门阵列和RAM宏小区或逻辑宏小区彼此可替换的区域。

4. 发明授权

US5306948A Semiconductor device and semiconductor module having auxiliary high power supplying terminals 失效
标题翻译：具有辅助高功率供电端子的半导体器件和半导体模块
公开(公告)号：US5306948A
公开(公告)日：1994-04-26
申请号：US950332
申请日：1992-09-24
申请人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
发明人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L21/66 , G01R1/04 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/498 , H01L25/065 , H01L23/02 , H01L23/12
CPC分类号： H01L25/0655 , G01R1/0483 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/49805 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152
摘要： Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.
摘要翻译：这里公开的是采用MCC结构的芯片载体型半导体器件，其中半导体芯片安装在基底表面上，并且其中与半导体芯片的外部端子连接的安装端子安装在后表面的基底。即使安装端子倍增或小型化，为了实现轻松便宜地进行测试，采用MCC结构的芯片载体型半导体器件配置在具有辅助端子的基底基板的电连接多个外部端子排列在半导体芯片的形成元件的主表面上。

5. 发明授权

US06760895B2 Design method of semiconductor device 有权
标题翻译：半导体器件的设计方法
公开(公告)号：US06760895B2
公开(公告)日：2004-07-06
申请号：US10147991
申请日：2002-05-20
申请人： Yuko Ito , Satoru Isomura
发明人： Yuko Ito , Satoru Isomura
IPC分类号： G06F945
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk. The method calculates the delay by using the total capacitance in consideration of the actual load after the layout and wiring, carries out the layout, wiring and modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the delay by using the total capacitance in consideration of the actual load and crosstalk, carries out the modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the crosstalk noise by using the total capacitance and coupling capacitance in consideration of the actual load, carries out the modification of wiring repeatedly until malfunctioning subsides, and uses data after the final layout and wiring for mask data.
摘要翻译：用于微处理器，ASIC和高速高性能LSI设计的半导体器件设计方法旨在提高延迟计算和串扰噪声计算的精度，并提高串扰和检查引起的延迟变化评估的准确性由串扰引起的故障。该方法通过考虑布线和布线后的实际负载，使用总电容来计算延迟，重复布线，布线和修改布线，直到目标周期内传输达到目标，通过使用总电容计算延迟考虑到实际负载和串扰，反复进行布线修改，直到目标周期内传输成为可能，考虑到实际负载，通过使用总电容和耦合电容来计算串扰噪声，执行布线改造重复直到故障消除，并在最终布局和掩模数据接线后使用数据。

6. 发明授权

US06530066B1 Method of computing wiring capacitance, method of computing signal propagation delay due to cross talk and computer-readable recording medium storing such computed data 有权
标题翻译：计算布线电容的方法，计算由串扰引起的信号传播延迟的方法以及存储这种计算数据的计算机可读记录介质
公开(公告)号：US06530066B1
公开(公告)日：2003-03-04
申请号：US09666863
申请日：2000-09-21
申请人： Yuko Ito , Satoru Isomura
发明人： Yuko Ito , Satoru Isomura
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio. Regarding a case of no adjacent wiring, the capacity depending on increase of crossing ratio has a high increase rate in comparison to a case of one-side or both-sides adjacent wiring.
摘要翻译：本发明提供一种计算布线电容的方法，其能够根据高速和高精度的布线获得寄生电容，并且提供一种计算由串扰引起的信号传播延迟的方法，以能够去除延迟预测时高速的剩余利润。在诸如微处理器等的LSI的设计中，关于改变相邻布线（（a）没有相邻布线，（b）单面相邻布线）的多个模型中的每一个模型确定每单位长度的总容量Ctotal，（c）两侧相邻布线）和/或交叉比（（i）0％，（ii）33％，（iii）67％和（iv）100％），由此形成文库以设计 LSI。关于该单位长度的总容量的特性，与交叉比的增加相关的容量在低交叉比的面积上具有高的增加率，而根据交叉比的增加的容量具有较高的增加率交叉比。关于没有相邻布线的情况，与一侧或两侧相邻布线的情况相比，与交叉比的增加相关的容量具有高的增加率。

7. 发明授权

US5396198A Electronic circuit device having a series connection of resistor and capacitance as a noise reducing circuit connected to a power source wiring 失效
标题翻译：具有连接到电源布线的降噪电路的电阻和电容的串联连接的电子电路装置
公开(公告)号：US5396198A
公开(公告)日：1995-03-07
申请号：US118178
申请日：1993-09-09
申请人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
发明人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
IPC分类号： H01L23/528 , H01L23/66 , H01P5/12 , H01P1/26
CPC分类号： H01L23/5286 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011
摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.
摘要翻译：电源线为构成电子电路装置的各电子线路供电。负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半电路。这些负载电路中的每一个都包括电阻和电容的串联电路。

8. 发明授权

US5661329A Semiconductor integrated circuit device including an improved separating groove arrangement 失效
标题翻译：半导体集成电路器件包括改进的分离槽布置
公开(公告)号：US5661329A
公开(公告)日：1997-08-26
申请号：US350944
申请日：1994-12-07
申请人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
发明人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/10 , H01L29/00 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/1079
摘要： A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.
摘要翻译：半导体集成电路器件包括分离形成为围绕要形成半导体元件的有源区的第一和第二沟槽的元件。此外，当从平面视图观察时，形成第三凹槽以围绕第一凹槽的至少一部分。在半导体集成电路器件中，硅层的有源区域和元件分离区域通过从硅层的主表面延伸到下面的绝缘层的分离槽彼此绝缘，并且被馈送有公共固定潜在。

9. 发明授权

US5428312A ECL interface circuit 失效
标题翻译： ECL接口电路
公开(公告)号：US5428312A
公开(公告)日：1995-06-27
申请号：US57827
申请日：1993-05-07
申请人： Keiichi Higeta , Satoru Isomura , Kazuhiro Akimoto
发明人： Keiichi Higeta , Satoru Isomura , Kazuhiro Akimoto
IPC分类号： G11C11/413 , H01L21/8244 , H01L27/11 , H03K19/003 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/086 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device has a circuit construction which is devised with an output circuit for feeding an output current to an operating supply voltage in response to an output signal of a current switch circuit responding to an input signal. A constant current element for producing the operating current of the current switch circuit is fed with a constant voltage through a resistance element. A capacitor is coupled between the input of the constant current element and the operating supply voltage so that it constructs a time constant circuit together with the resistance element. The time constant circuit has a time constant set longer than the period of the output signal of the output circuit.
摘要翻译：半导体集成电路器件具有电路结构，该电路结构用于响应于电流开关电路响应于输入信号的输出信号，输出电路将输出电流馈送到工作电源电压。用于产生电流开关电路的工作电流的恒流元件通过电阻元件被馈送恒定电压。电容器耦合在恒流元件的输入端和工作电源电压之间，从而与电阻元件一起构成时间常数电路。时间常数电路具有比输出电路的输出信号的周期长的时间常数。

10. 发明授权

US4959704A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4959704A
公开(公告)日：1990-09-25
申请号：US198311
申请日：1988-05-25
申请人： Satoru Isomura , Masato Iwabuchi , Katsumi Ogiue
发明人： Satoru Isomura , Masato Iwabuchi , Katsumi Ogiue
IPC分类号： H01L21/60 , H01L21/82 , H01L21/822 , H01L23/057 , H01L25/065 , H01L25/18 , H01L27/04 , H01L27/118
CPC分类号： H01L24/05 , H01L23/057 , H01L24/03 , H01L24/11 , H01L25/0652 , H01L25/18 , H01L27/118 , H01L27/11898 , H01L2224/0401 , H01L2224/04042 , H01L2224/05138 , H01L2224/11474 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L24/12 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01045 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/351 , Y10S257/903
摘要： In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.
摘要翻译：在具有RAM的门阵列中，配置互连逻辑部分和门阵列的I / O单元电路的旁路信号线，以便在RAM的上方延伸。为了最小化相互干扰，从与旁路信号线相邻的层形成的信号线被设置成与直角信号线相交。此外，设置彼此平行延伸的不同层中的互连间距，使得差分感测电路中的噪声被消除。

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