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1. 发明授权

US07187227B2 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US07187227B2
公开(公告)日：2007-03-06
申请号：US10636381
申请日：2003-08-06
申请人： Yohtaro Umeda , Atsushi Kanda
发明人： Yohtaro Umeda , Atsushi Kanda
IPC分类号： H03K17/284
CPC分类号： H03K17/04123 , H03K17/102
摘要： A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.
摘要翻译：驱动器电路包括第一和第二三端有源元件以及第一和第二延迟单元。第一和第二三端有源元件串联连接。第一和第二三端有源元件中的每一个具有放大功能和第一，第二和第三电极。每个三端有源元件的第二和第三电极串联连接在第一和第二电位之间。第一和第二延迟单元接收相同的输入信号。第一和第二延迟单元的输出分别连接到第一和第二三端有源元件的第一电极。第二延迟单元的延迟量大于第一延迟单元的延迟量。第一延迟单元的延迟量是包括零的有限值。

2. 发明申请

US20050046025A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050046025A1
公开(公告)日：2005-03-03
申请号：US10962735
申请日：2004-10-12
申请人： Atsushi Kanda
发明人： Atsushi Kanda
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/4763 , H01L21/60 , H01L23/485 , H01L29/76
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05073 , H01L2224/05599 , H01L2224/05624 , H01L2224/13099 , H01L2224/13144 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.
摘要翻译：实施例包括半导体器件，包括：焊盘，其形成在绝缘层上并具有与外部部件的电连接区域; 以及保护绝缘层，其具有用于暴露电连接区域的孔。保护绝缘层可以包括第一绝缘层和第二绝缘层，并且这些绝缘层的侧表面暴露于孔。围绕电连接区域的侧表面的至少一部分具有与衬垫顶表面成锐角的锥形构型。该半导体器件不仅能够减少制造步骤，而且还为具有足够的厚度和应力松弛特性的焊盘提供可靠的钝化结构。

3. 发明授权

US06638804B2 Method of manufacturing semiconductor device with high and low breakdown transistors 失效
标题翻译：制造具有高和低击穿晶体管的半导体器件的方法
公开(公告)号：US06638804B2
公开(公告)日：2003-10-28
申请号：US10271536
申请日：2002-10-17
申请人： Atsushi Kanda , Yasushi Haga
发明人： Atsushi Kanda , Yasushi Haga
IPC分类号： H01L218238
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L21/823857 , H01L21/823864 , H01L21/823892
摘要： Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15B is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be formed efficiently on an identical substrate without damaging the characteristics of the respective MOS transistors.
摘要翻译：在形成在基板100上的第一和第二氧化膜110和112中，低击穿电压晶体管区域LV中的氧化膜全部被蚀刻掉，而在高击穿电压晶体管区域中的氧化膜的整个表面 HV完好无损。随后在基板100的整个表面上形成用于限定侧壁的第六氧化物膜119，并且在整个高击穿电压晶体管区域HV上形成抗蚀剂R17。执行低击穿电压晶体管区域LV的过蚀刻，以使衬底100的表面暴露并仅在低击穿电压晶体管区域LV中限定侧壁。使氧化物膜119保持在高击穿电压晶体管区域HV中。然后用抗蚀剂R15B蚀刻掉氧化膜119和112的非必需部分。这导致预期形成漏极区域和源极区域的漏极 - 源极形成区域在高击穿电压nMOS区域HVn中的元件形成区域中断开。抗蚀剂R15B不被去除，而是连续使用，并且n型杂质离子注入到开漏源形成区域中。这种布置使得能够在相同的衬底上有效地形成高击穿电压MOS晶体管和低击穿电压MOS晶体管，而不损害各个MOS晶体管的特性。

4. 发明授权

US06455726B2 Manufacturing method 有权
标题翻译：制造方法
公开(公告)号：US06455726B2
公开(公告)日：2002-09-24
申请号：US09782291
申请日：2001-02-14
申请人： Masaharu Ichihara , Norio Hashimoto , Atsushi Kanda , Kooji Kagara
发明人： Masaharu Ichihara , Norio Hashimoto , Atsushi Kanda , Kooji Kagara
IPC分类号： C07C22900
CPC分类号： C07C227/06 , C07C229/38 , C07C229/34
摘要： A compound of the following formula (II) and a process for preparing of the compound of the following formula (I) its preparation wherein R1 is carboxy or protected carboxy; R2 is lower alkoxy or higher alkoxy; A1 is a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane; and A2 is a divalent aromatic ring, a divalent heterocyclic group or a divalent cyclo(lower)alkane, or a salt thereof. The process comprises, reacting a compound of the formula (III): wherein R1, R2, A1 and A2 are each as defined above or a salt thereof, with an acid ammonium salt to give a compound of the formula (II).
摘要翻译：下式（II）的化合物及其制备方法，其中R1为羧基或被保护的羧基; R2为低级烷氧基或高级烷氧基; A1为二价芳环，二价杂环基团或二价环（低级）烷烃; 和A 2是二价芳环，二价杂环基或二价环（低级）烷烃或其盐。该方法包括使式（III）化合物：其中R1，R2，A1和A2各自如上定义，或其盐与酸性铵盐反应，得到式（II）化合物。

5. 发明授权

US06916714B2 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, IN WHICH A HIGH-BREAKDOWN-VOLTAGE MOS TRANSISTOR AND A LOW-BREAKDOWN-VOLTAGE MOS TRANSISTOR ARE FORMED ON AN IDENTICAL SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY 失效
标题翻译：制造半导体器件的方法，其中形成高标准电压MOS晶体管和低突变电压MOS晶体管形成在标识半导体衬底和制造的半导体器件上
公开(公告)号：US06916714B2
公开(公告)日：2005-07-12
申请号：US10210053
申请日：2002-08-02
申请人： Atsushi Kanda , Yasushi Haga
发明人： Atsushi Kanda , Yasushi Haga
IPC分类号： H01L21/266 , H01L21/8238 , H01L27/02 , H01L27/092 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L27/0266
摘要： A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be efficiently formed on an identical substrate without damaging the characteristics of the respective transistors.
摘要翻译：根据本发明的制造半导体器件的步骤首先在形成在衬底上的栅极氧化膜的中心部分上形成栅电极，在包括栅电极的衬底的整个表面上形成氧化硅膜，并且蚀刻氧化硅膜的整个表面，以便在栅电极的侧面上形成氧化硅膜的侧壁。然后，该过程根据目标MOS晶体管的沟道注入杂质离子，以指定漏极区域和源极区域。在规定漏极区域和源极区域的过程中，预先在高耐压MOS晶体管的栅极氧化膜的至少周边部分形成抗蚀剂，以防止将杂质离子注入栅极氧化膜的周边部分下方的下层区域。这种布置使得高耐压MOS晶体管和低击穿电压MOS晶体管能够在相同的衬底上有效地形成，而不损害各个晶体管的特性。

6. 发明授权

US06720222B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06720222B2
公开(公告)日：2004-04-13
申请号：US10271589
申请日：2002-10-17
申请人： Atsushi Kanda , Yasushi Haga
发明人： Atsushi Kanda , Yasushi Haga
IPC分类号： H01L21336
CPC分类号： H01L27/0922 , H01L21/823814 , H01L21/823857
摘要： Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region. This arrangement enables both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor to be formed efficiently on an identical substrate without damaging the characteristics of the respective MOS transistors.
摘要翻译：在形成在基板100上的第一和第二氧化膜110和112中，低击穿电压晶体管区域LV中的氧化膜全部被蚀刻掉，而在高击穿电压晶体管区域中的氧化膜的整个表面 HV完好无损。随后在基板100的整个表面上形成大约为标准厚度大约2000埃的较大厚度的用于限定侧壁的第六氧化膜119。第六氧化膜119的过蚀刻限定侧壁119SW。然后用抗蚀剂R15A蚀刻掉氧化膜112的非必需部分。这导致预期形成漏极区域和源极区域的漏极 - 源极形成区域在高击穿电压nMOS区域HVn中的元件形成区域中断开。抗蚀剂R15A不被去除，而是连续使用，并且n型杂质离子注入到开漏源形成区域中。这种布置使得能够在相同的衬底上有效地形成高击穿电压MOS晶体管和低击穿电压MOS晶体管，而不损害各个MOS晶体管的特性。

7. 发明授权

US06355800B1 Process for producing aminopiperazine derivatives 失效
标题翻译：制备氨基哌嗪衍生物的方法
公开(公告)号：US06355800B1
公开(公告)日：2002-03-12
申请号：US09509812
申请日：2000-04-06
申请人： Kooji Kagara , Norio Hashimoto , Atsushi Kanda , Yukihisa Baba , Tetsuo Furutera
发明人： Kooji Kagara , Norio Hashimoto , Atsushi Kanda , Yukihisa Baba , Tetsuo Furutera
IPC分类号： C07D29532
CPC分类号： C07D295/32
摘要： A new industrial process excellent in yield and purity for preparing a compound of the formula: or a salt thereof in a less number of steps with a synthetic pathway without proceeding via nitroso compounds, wherein R1 is lower aryl, ar(lower)alkoxy or heterocyclic group, each of which may be substituted with halogen, and R2 is cyclo(lower)alkyl, aryl or ar(lower)alkyl, each of which may be substituted with halogen.
摘要翻译：一种新的工业方法，其具有优良的产率和纯度，用于通过合成途径制备下式化合物或其盐在较少数量的步骤中，而不经由亚硝基化合物进行，其中R 1为低级芳基，芳（低级）烷氧基或杂环基团，其各自可以被卤素取代，并且R 2是环（低级）烷基，芳基或芳（低级）烷基，其各自可以被卤素取代。

8. 发明授权

US5656113A Method of manufacturing a multilayered wiring substrate of aluminum nitride having a high dielectric layer 失效
标题翻译：制造具有高介电层的氮化铝多层布线基板的方法
公开(公告)号：US5656113A
公开(公告)日：1997-08-12
申请号：US492441
申请日：1995-06-19
申请人： Tatsuya Ikeda , Atsushi Kanda
发明人： Tatsuya Ikeda , Atsushi Kanda
IPC分类号： H05K3/46 , C04B35/581 , C04B41/51 , C04B41/88 , H01L21/48 , H05K1/03 , H05K1/16 , B32B31/26
CPC分类号： C04B41/009 , C04B35/581 , C04B41/5194 , C04B41/88 , H01L21/4807 , H01L21/4857 , H05K1/162 , H05K1/0306 , H05K1/16 , H05K3/4611 , H05K3/4629 , H05K3/4688 , Y10T156/1056 , Y10T428/24942
摘要： An aluminum nitride multilayered wiring substrate and a method of manufacturing the wiring substrate are provided. The wiring substrate is provided with the high dielectric layer. Although the wiring substrate has no excessively multilayered structure, high capacitance can be easily obtained. The multilayered wiring substrate is a laminated body of an upper substrate layer, a capacitor layer and a lower substrate layer. Three aluminum nitride Layers composing the upper substrate layer have interior peripheries arranged in a step fashion stepping down toward the center of the multilayered wiring substrate. The central part of the upper substrate layer is thinner than the periphery. The surfaces and inside of the upper substrate layer are provided with conductive layers. The capacitor layer is a laminated body of two high dielectric layers formed of aluminum nitride with titanium nitride added thereto for raising the specific dielectric constant. Conductive layers are also formed on both surfaces of the capacitor layer and on the interface between the high dielectric layers. The lower substrate layer is also a laminated body of two aluminum nitride layers.
摘要翻译：提供一种氮化铝多层布线基板及其制造方法。布线基板设置有高介电层。虽然布线基板没有过多的结构，但是容易获得高电容。多层布线基板是上基板层，电容层和下基板层的层叠体。构成上基板层的三个氮化铝层具有沿着多层布线基板的中心向下逐步排列的内周。上基板层的中心部分比周边薄。上基板层的表面和内部设有导电层。电容器层是由氮化铝和氮化钛形成的两个高电介质层的叠层体，其中添加有氮化钛以提高比介电常数。导电层也形成在电容器层的两个表面和高介电层之间的界面上。下基板层也是两个氮化铝层的层叠体。

9. 发明授权

US5589429A Aluminum nitride sintered body and process for producing the same 失效
标题翻译：氮化铝烧结体及其制造方法
公开(公告)号：US5589429A
公开(公告)日：1996-12-31
申请号：US364497
申请日：1994-12-27
申请人： Kenzo Kawaguchi , Tetsuya Takemura , Hideki Matsubara , Sinya Takagi , Atsushi Kanda
发明人： Kenzo Kawaguchi , Tetsuya Takemura , Hideki Matsubara , Sinya Takagi , Atsushi Kanda
IPC分类号： C04B35/581 , C04B35/58
CPC分类号： C04B35/581
摘要： An aluminum nitride sintered body comprising aluminum nitride as a main component, a titanium compound, and an yttrium compound, wherein when the content of titanium and the content of yttrium both in terms of percentage by weight based on the aluminum nitride sintered body are plotted on an x-y coordinate system, with the titanium content as the x axis and the yttrium content as the y axis, the titanium content and the yttrium content each is within a region surrounded by the lines connecting points A and B, B and C, C and D, D and E, and E and A, inclusive of the lines the points A, B, C, D and E being:A (0.2, 2.0)B (0.2, 6.5)C (1.0, 10.25)D (2.2, 10.25)E (2.2, 5.0).
摘要翻译：一种以氮化铝为主要成分的铝氮化物烧结体，钛化合物和钇化合物，其中当钛含量和钇含量以氮化铝烧结体为基准的重量百分数表示在 xy坐标系，钛含量为x轴，钇含量为y轴，钛含量和钇含量各自在连接点A和B，B和C，C和 A，B，C，D和E分别为：A（0.2,2.0）B（0.2,6.5）C（1.0,10.25）D（2.2， 10.25）E（2.2,5.0）。

10. 发明授权

US4657825A Electronic component using a silicon carbide substrate and a method of making it 失效
标题翻译：使用碳化硅衬底的电子元件及其制造方法
公开(公告)号：US4657825A
公开(公告)日：1987-04-14
申请号：US812634
申请日：1985-12-23
申请人： Atsushi Kanda , Shunichi Takagi , Rokuro Kambe
发明人： Atsushi Kanda , Shunichi Takagi , Rokuro Kambe
IPC分类号： C04B41/52 , C04B41/89 , H05K1/03 , H05K3/38 , B32B15/04
CPC分类号： C04B41/009 , C04B41/52 , C04B41/89 , C04B2111/00844 , H05K1/0306 , H05K3/38 , Y10T428/12576 , Y10T428/12674 , Y10T428/12806 , Y10T428/12812 , Y10T428/12826 , Y10T428/12875 , Y10T428/12882 , Y10T428/12889 , Y10T428/12896
摘要： The bond strength between a silicon carbide substrate and a metal layer comprised of a series of metal films is improved without detrimentally affecting other properties of such a device by interposing a layer of silicon, Si.sub.2 Mo or mixtures thereof between the substrate and the first metal film in the layer which is preferably Ti, Zr or Hf.
摘要翻译：通过在衬底和第一金属膜之间插入一层硅，Si 2 Mo或其混合物，改善碳化硅衬底和由一系列金属膜组成的金属层之间的结合强度，而不会有害地影响这种器件的其它性能该层优选为Ti，Zr或Hf。

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