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1. 发明授权

US07456681B2 Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit 有权
标题翻译：电源电压降压电路，延迟电路和具有延迟电路的半导体器件
公开(公告)号：US07456681B2
公开(公告)日：2008-11-25
申请号：US11360522
申请日：2006-02-24
申请人： Atsunori Hirobe , Toru Ishikawa
发明人： Atsunori Hirobe , Toru Ishikawa
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , H03K5/133 , H03K2005/00032 , H03K2005/0013
摘要： A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.
摘要翻译：延迟电路具有由NMOS或PMOS晶体管主导的电路结构。延迟电路具有作为电源电压的电源电压降压电路的输出电压，该电源电压降压电路具有用于产生通过偏移电压和制造变化相关电压获得的参考电压的电平发生电路，并且m 时间电压发生电路。半导体器件包括延迟电路。

2. 发明申请

US20060192610A1 Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit 有权
标题翻译：电源电压降压电路，延迟电路和具有延迟电路的半导体器件
公开(公告)号：US20060192610A1
公开(公告)日：2006-08-31
申请号：US11360522
申请日：2006-02-24
申请人： Atsunori Hirobe , Toru Ishikawa
发明人： Atsunori Hirobe , Toru Ishikawa
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , H03K5/133 , H03K2005/00032 , H03K2005/0013
摘要： A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.
摘要翻译：延迟电路具有由NMOS或PMOS晶体管主导的电路结构。延迟电路具有作为电源电压的电源电压降压电路的输出电压，该电源电压降压电路具有用于产生通过偏移电压和制造变化相关电压获得的参考电压的电平发生电路，并且m 时间电压发生电路。半导体器件包括延迟电路。

3. 发明申请

US20110188330A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110188330A1
公开(公告)日：2011-08-04
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

4. 发明授权

US07876637B2 Semiconductor device and memory 有权
标题翻译：半导体器件和存储器
公开(公告)号：US07876637B2
公开(公告)日：2011-01-25
申请号：US11935639
申请日：2007-11-06
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147 , G11C11/4074
摘要： A semiconductor device of the present invention comprises a first step-down voltage circuit to generate a first step-down voltage lower than an externally-supplied power supply voltage, and a second step-down voltage circuit to generate a second step-down voltage lower than the first step-down voltage. The first step-down voltage circuit has a withstand voltage no lower than the power supply voltage and the second step-down voltage circuit has a withstand voltage no lower than the first step-down voltage.
摘要翻译：本发明的半导体器件包括：第一降压电路，用于产生比外部提供的电源电压低的第一降压电压;以及第二降压电路，以产生较低的第二降压电压比第一降压电压。第一降压电路具有不低于电源电压的耐受电压，而第二降压电路具有不低于第一降压电压的耐受电压。

5. 发明授权

US07724588B2 Overdrive write method, write amplifier power generating circuit, and semiconductor memory device including the same 有权
标题翻译：超速写入方法，写入放大器发生电路和包括其的半导体存储器件
公开(公告)号：US07724588B2
公开(公告)日：2010-05-25
申请号：US11671259
申请日：2007-02-05
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/1078 , G11C7/1096 , G11C11/4096
摘要： A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).
摘要翻译：写放大器功率产生电路包括用于改变输出电压的控制单元。在一对位线被放大的第一写入周期中，写入操作是由写入放大器的高电平被设置为第一电压（例如，电源电压）的过驱动写入方法执行的，。在一对位线中的放大之后的第二写入周期已经完成时，通过写入方法执行写入操作，其中写入放大器的高电平被设置为第二电压（例如，内部电压）。

6. 发明授权

US08391087B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08391087B2
公开(公告)日：2013-03-05
申请号：US13164472
申请日：2011-06-20
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/1048 , G11C7/22 , G11C11/4076
摘要： A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area.
摘要翻译：一种半导体器件包括：公共布置的用于传送写入数据和读取数据的多个存储器阵列基本单元，第二总线传送地址/命令，接收传送到第二总线的地址/命令的多个第一缓冲器电路的双向第一总线，其中用于产生所述地址/命令的控制延迟以及为所述第一总线准备用于写访问的写入数据和用于输出读取数据的输出延迟都被设置为大于或等于用于写入或读取数据的选择时间的长度所选区域的存储单元。

7. 发明申请

US20090010081A1 OVERDRIVE WRITE METHOD, WRITE AMPLIFIER POWER GENERATING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：放大写入方法，写放大器发电电路和包括其的半导体存储器件
公开(公告)号：US20090010081A1
公开(公告)日：2009-01-08
申请号：US11671259
申请日：2007-02-05
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/4091 , G11C7/1078 , G11C7/1096 , G11C11/4096
摘要： A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).
摘要翻译：写放大器功率产生电路包括用于改变输出电压的控制单元。在一对位线被放大的第一写入周期中，写入操作是由写入放大器的高电平被设置为第一电压（例如，电源电压）的过驱动写入方法执行的，。在一对位线中的放大之后的第二写入周期已经完成时，通过写入方法执行写入操作，其中写入放大器的高电平被设置为第二电压（例如，内部电压）。

8. 发明授权

US06525575B2 Output buffer circuit 有权
公开(公告)号：US06525575B2
公开(公告)日：2003-02-25
申请号：US09892068
申请日：2001-06-25
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： H03K300
CPC分类号： H03K17/693 , H03K19/01742
摘要： An output buffer circuit (300) having an output time which may be reduced is provided. The output buffer circuit (300) can include a selector (1), a precharge circuit (2) and a buffer (3). Selector (1) can be responsive to a control signal (SELB) and may provide data on a data signal line (9). Precharge circuit (2) may be responsive to control signal (SELB) and may precharge data signal line (9) to a first potential when control signal is in a disable state. Selector (1) may electrically disconnect data input terminals (4 and 5) from data signal line (9) when control signal (SELB) is in the disable state. Buffer (3) may output a logic value from the data signal line (9) when control signal (SELB) is in an enable state.

9. 发明授权

US08335116B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08335116B2
公开(公告)日：2012-12-18
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/00 , G11C8/00 , G11C8/16
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

10. 发明申请

US20060203568A1 Overdrive period control device and overdrive period determining method 有权
标题翻译：过驱动时段控制装置和过驱动时段确定方法
公开(公告)号：US20060203568A1
公开(公告)日：2006-09-14
申请号：US11373133
申请日：2006-03-13
申请人： Atsunori Hirobe
发明人： Atsunori Hirobe
IPC分类号： G11C7/10
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/08 , G11C11/4074 , G11C2207/065
摘要： An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit supplying a power source voltage to the other terminal of the delay element at the input timing of a signal from the outside and raising the potential at the node to the power source voltage; and a comparison circuit comparing the potential at the node with a reference potential and detecting the timing at which both levels of the potentials coincide. The device outputs a signal indicating a period determined by the input timing of the signal from the outside and the timing in which the comparison circuit detects that the levels coincide.
摘要翻译：过驱动时段控制装置包括连接到其上检测到电位的节点的预充电电路，并且用于将节点处的电位提高到第一电位; 延迟元件，其一个端子连接到节点; 在来自外部的信号的输入定时将电源电压提供给延迟元件的另一端的充电电路，并将节点处的电位提高到电源电压; 以及比较电路，将节点的电位与参考电位进行比较，并检测电位的两个电平一致的时刻。该装置输出指示由来自外部的信号的输入定时确定的周期的信号和比较电路检测到电平一致的定时。

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