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1. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

2. 发明授权

US08417965B1 Method and circuit for secure definition and integration of cores 有权
标题翻译：核心的安全定义和集成的方法和电路
公开(公告)号：US08417965B1
公开(公告)日：2013-04-09
申请号：US12755760
申请日：2010-04-07
申请人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
发明人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , G06F9/445 , H04L29/06 , H04L9/00 , H04L9/30 , H04K1/00 , H04N7/16
CPC分类号： G06F17/505 , G06F11/3664 , G06F17/5054 , H04L9/0825 , H04L9/0877 , H04L63/0478
摘要： An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
摘要翻译：本发明的一个实施例提供了一种用于将核心安全地定义和集成到电路设计中而不暴露核心的方法和电路。在一个实施例中，获得核心开发包。核心开发包包括加密核心和加密核心的解密密钥。解密密钥用非对称密码加密。加密核心从设计工具传输到可信平台模块。解密密钥用非对称密码的私钥解密。加密核心在可信平台模块内被解密。使用解密的核执行一个或多个设计工具操作。

3. 发明授权

US08868396B1 Verification and debugging using heterogeneous simulation models 有权
标题翻译：使用异构仿真模型进行验证和调试
公开(公告)号：US08868396B1
公开(公告)日：2014-10-21
申请号：US12605077
申请日：2009-10-23
申请人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
发明人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
摘要翻译：本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分设计负责的差异。

4. 发明授权

US08102188B1 Method of and system for implementing a circuit in a device having programmable logic 有权
标题翻译：用于在具有可编程逻辑的设备中实现电路的方法和系统
公开(公告)号：US08102188B1
公开(公告)日：2012-01-24
申请号：US12757770
申请日：2010-04-09
申请人： Chi Bun Chan , Nabeel Shirazi
发明人： Chi Bun Chan , Nabeel Shirazi
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.
摘要翻译：公开了一种在具有可编程资源和预定量的可用内部存储器的设备中实现电路的方法。该方法包括利用电路设计来配置设备的可编程资源; 将第一页数据存储在随机存取存储器块中; 当实现电路设计时，确定页面错误同时与随机存取存储器块接口; 执行所述设备的部分重新配置，其中第二数据页被存储在所述随机存取存储器块中; 并访问第二页数据。还公开了一种在具有可编程逻辑的设备中实现电路的系统。

5. 发明授权

US08402442B1 Common debugger method and system 有权
标题翻译：常用的调试器方法和系统
公开(公告)号：US08402442B1
公开(公告)日：2013-03-19
申请号：US12510810
申请日：2009-07-28
申请人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/267 , G06F11/3664
摘要： Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.
摘要翻译：公开了用于操作多个调试器工具的方法。一个常见的调试器接收第一个类型的命令进行处理。每个first-type命令引用一个调试器工具。每个调试器工具提供对电子系统的一个或多个组件的相应集合的控制，并识别相应的一组工具特定命令。每个输入第一类型命令被转换成与第一类型命令中指定的调试器工具兼容的相应的特定于工具的命令。来自公共调试器的每个相应的特定于工具的命令被提供给转换相应的特定于工具的命令的输入第一类型命令中指定的调试器工具之一。每个翻译的特定于工具的命令都由目标调试工具执行。

6. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

7. 发明授权

US07636653B1 Point-to-point ethernet hardware co-simulation interface 有权
标题翻译：点到点以太网硬件协同仿真界面
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译：与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。

8. 发明授权

US08265918B1 Simulation and emulation of a circuit design 有权
标题翻译：电路设计的仿真和仿真
公开(公告)号：US08265918B1
公开(公告)日：2012-09-11
申请号：US12579846
申请日：2009-10-15
申请人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
发明人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.
摘要翻译：协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步运行。

9. 发明授权

US07937259B1 Variable clocking in hardware co-simulation 有权
标题翻译：硬件协同仿真可变时钟
公开(公告)号：US07937259B1
公开(公告)日：2011-05-03
申请号：US12002838
申请日：2007-12-18
申请人： Chi Bun Chan , Bradley L. Taylor , Nabeel Shirazi
发明人： Chi Bun Chan , Bradley L. Taylor , Nabeel Shirazi
IPC分类号： G06F9/455
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.
摘要翻译：公开了共模拟系统的各种实施例。在一个实施例中，数据处理装置执行模拟电子电路设计的第一块的模拟器。第一时钟源产生第一时钟信号，第二时钟源产生第二时钟信号。第一和第二时钟信号彼此独立，并且第二时钟信号的工作频率可以从时钟控制接口动态地调整。可编程逻辑器件（PLD）配置有逻辑，逻辑包括由第一时钟信号定时的协同仿真接口，由第二时钟信号计时的电子电路设计的第二块，以及控制数字传输的同步器共模仿界面和第二块。

10. 发明授权

US07747423B1 Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain 有权
标题翻译：在边界扫描链中利用多个PLD进行协同仿真的系统和方法
公开(公告)号：US07747423B1
公开(公告)日：2010-06-29
申请号：US11527841
申请日：2006-09-27
申请人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
发明人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
摘要翻译：使用耦合在一起以形成边界扫描链的多个可编程逻辑器件（PLD）执行分割电路设计的协同仿真的系统和方法。主机通过编程电缆耦合到扫描链。主计算机上的驻留是与电路设计中的块对应的运行时协同仿真块，其中每个块被指定为在扫描链中的一个PLD上运行; 与编程电缆接口的编程电缆设备驱动器; 和代理组件。代理组件耦合到所有运行时协同仿真模块和编程电缆设备驱动程序。每个共模拟块包括唯一的模式标识符，其也存在于相关联的PLD中。使用此模式标识符，可以从扫描链中提取针对特定PLD的数据和命令，同时忽略针对扫描链中其他PLD的数据和命令。

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