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1. 发明授权

US08080439B2 Method of making a vertical phase change memory (PCM) and a PCM device 有权
标题翻译：制造垂直相变存储器（PCM）和PCM装置的方法
公开(公告)号：US08080439B2
公开(公告)日：2011-12-20
申请号：US12039371
申请日：2008-02-28
申请人： Arturo M. Martinez, Jr. , Rajesh A. Rao
发明人： Arturo M. Martinez, Jr. , Rajesh A. Rao
IPC分类号： H01L21/00 , H01L21/06 , H01L21/8234 , H01L21/20
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , Y10T428/24479
摘要： A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
摘要翻译：制造相变随机存取存储器（PCM）装置的方法包括形成包括加热器层，相变材料层和顶部电极层的PCM堆叠。顶层保护层形成在PCM叠层上。然后将顶部保护层和PCM堆叠的第一部分图案化，其中PCM堆叠的第一部分排除加热器层。沿图案化的顶部保护层和PCM堆叠的第一部分的侧壁形成侧壁保护特征。使用（i）侧壁保护特征和（ii）图案化顶部保护层和PCM堆叠的第一部分一起作为掩模来蚀刻加热器层，以形成PCRAM堆叠的自对准加热器层底部电极，由此完成 PCRAM设备的存储器位。

2. 发明申请

US20090220744A1 METHOD OF MAKING A VERTICAL PHASE CHANGE MEMORY (PCM) AND A PCM DEVICE 有权
标题翻译：制造垂直相变记忆体（PCM）和PCM装置的方法
公开(公告)号：US20090220744A1
公开(公告)日：2009-09-03
申请号：US12039371
申请日：2008-02-28
申请人： Arturo M. Martinez, JR. , Rajesh A. Rao
发明人： Arturo M. Martinez, JR. , Rajesh A. Rao
IPC分类号： B32B3/00 , H01B13/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , Y10T428/24479
摘要： A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
摘要翻译：制造相变随机存取存储器（PCM）装置的方法包括形成包括加热器层，相变材料层和顶部电极层的PCM堆叠。顶层保护层形成在PCM叠层上。然后将顶部保护层和PCM堆叠的第一部分图案化，其中PCM堆叠的第一部分排除加热器层。沿图案化的顶部保护层和PCM堆叠的第一部分的侧壁形成侧壁保护特征。使用（i）侧壁保护特征和（ii）图案化顶部保护层和PCM堆叠的第一部分一起作为掩模来蚀刻加热器层，以形成PCRAM堆叠的自对准加热器层底部电极，由此完成 PCRAM设备的存储器位。

3. 发明授权

US08803217B2 Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode 有权
标题翻译：形成包括控制栅电极，半导体层和选择栅电极的电子器件的工艺
公开(公告)号：US08803217B2
公开(公告)日：2014-08-12
申请号：US11685297
申请日：2007-03-13
申请人： Rajesh A. Rao , Ramachandran Muralidhar
发明人： Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.
摘要翻译：包括非易失性存储单元的电子设备可以包括包括第一部分和第二部分的基板，其中第一部分内的第一主表面位于比第二部分内的第二主表面低的高度处。电子设备还可以包括覆盖第一部分的电荷存储堆叠，其中电荷存储堆叠包括不连续的存储元件。电子器件还可以包括覆盖第一部分的控制栅电极和覆盖第二部分的选择栅电极，其中选择栅电极包括侧壁间隔物。在特定实施例中，可以使用一种工艺来形成电荷存储堆和控制栅电极。在形成电荷存储堆和控制栅电极之后可以形成半导体层，以在不同的高度实现具有不同主表面的衬底。选择栅电极可以形成在半导体层上。

4. 发明授权

US08097873B2 Phase change memory structures 有权
标题翻译：相变记忆结构
公开(公告)号：US08097873B2
公开(公告)日：2012-01-17
申请号：US12881678
申请日：2010-09-14
申请人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
发明人： Ramachandran Muralidhar , Tushar P. Merchant , Rajesh A. Rao
IPC分类号： H01L29/04 , H01L45/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
摘要翻译：相变存储单元具有第一电极，多个柱和第二电极。多个柱与第一电极电耦合。每个支柱包括相变材料部分和加热器材料部分。第二电极电耦合到每个支柱。在一些示例中，支柱具有小于20纳米的宽度。

5. 发明授权

US07800164B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

6. 发明授权

US07416945B1 Method for forming a split gate memory device 有权
标题翻译：用于形成分离栅极存储器件的方法
公开(公告)号：US07416945B1
公开(公告)日：2008-08-26
申请号：US11676403
申请日：2007-02-19
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521
摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
摘要翻译：一种方法形成分离栅极存储器件。将衬底上的选择栅极材料层图案化以形成第一侧壁。邻近第一侧壁形成牺牲隔离物。纳米团簇形成在包括在牺牲间隔物上的衬底上。在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

7. 发明申请

US20080179658A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE TRANSISTORS, NON-VOLATILE MEMORY TRANSISTORS, AND LOGIC TRANSISTORS 有权
标题翻译：制造具有高电压晶体管的半导体器件，非易失性存储器晶体管和逻辑晶体管的方法
公开(公告)号：US20080179658A1
公开(公告)日：2008-07-31
申请号：US11627725
申请日：2007-01-26
申请人： Rajesh A. Rao , Ramachandran Muralidhar
发明人： Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L29/7887
摘要： A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.
摘要翻译：在半导体衬底上制造半导体器件。第一绝缘层形成在半导体衬底上，用作半导体衬底的第一区域中的高电压晶体管的栅极电介质。在形成第一绝缘层之后，在半导体衬底上形成第二绝缘层，用作在衬底的第二区域中用作非易失性存储晶体管的栅极电介质。在形成第二绝缘层之后，在半导体衬底上形成第三绝缘层，用作衬底的第三区域中用于逻辑晶体管的栅极电介质。

8. 发明申请

US20070202645A1 METHOD FOR FORMING A DEPOSITED OXIDE LAYER 审中-公开
标题翻译：形成沉积氧化层的方法
公开(公告)号：US20070202645A1
公开(公告)日：2007-08-30
申请号：US11680121
申请日：2007-02-28
申请人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
发明人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L21/8242
CPC分类号： H01L29/7885 , B82Y10/00 , H01L21/02164 , H01L21/02271 , H01L21/02304 , H01L21/02337 , H01L21/31612 , H01L29/40117 , H01L29/42332 , H01L29/7883
摘要： An oxide layer formed by deposition is subject to a treatment process to repair bond defects of the oxide layer. In one embodiment, the layer is treated with nitric oxide. In one embodiment, a nitric oxide gas is flowed over the dielectric layer at an elevated temperature. In still another embodiment, the oxide layer is treated with fluorine. A layer is deposited over the oxide layer and a species containing fluorine is ion implanted into the layer. The wafer is heated where the species is driven to the oxide layer.
摘要翻译：通过沉积形成的氧化物层经受处理工艺以修复氧化物层的结合缺陷。在一个实施方案中，该层用一氧化氮处理。在一个实施方案中，一氧化氮气体在升高的温度下流过电介质层。在另一个实施方案中，用氟处理氧化物层。在氧化物层上沉积一层，并且将含氟物质离子注入到该层中。加热晶片，将物质驱动到氧化物层。

9. 发明授权

US07186616B2 Method of removing nanoclusters in a semiconductor device 有权
标题翻译：在半导体器件中去除纳米团簇的方法
公开(公告)号：US07186616B2
公开(公告)日：2007-03-06
申请号：US11082094
申请日：2005-03-16
申请人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle
发明人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/30604 , H01L21/3065 , H01L29/42332 , H01L29/66825
摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400–900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device at a temperature in a range of 400–900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanociusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.
摘要翻译：一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件在400-900摄氏度的温度范围内。在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米过滤器中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层层。

10. 发明授权

US07091130B1 Method of forming a nanocluster charge storage device 有权
标题翻译：形成纳米团簇电荷存储装置的方法
公开(公告)号：US07091130B1
公开(公告)日：2006-08-15
申请号：US10876820
申请日：2004-06-25
申请人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle , Gowrishankar L. Chindalore
发明人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle , Gowrishankar L. Chindalore
IPC分类号： H01I21/302
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译：通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。第二形成的含多晶硅的层从包含多个存储单元的区域中去除。在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

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