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1. 发明申请

US20040134769A1 Partially filling copper seed layer 有权
标题翻译：部分填充铜籽层
公开(公告)号：US20040134769A1
公开(公告)日：2004-07-15
申请号：US10428476
申请日：2003-05-01
申请人： Applied Materials, Inc.
发明人： Wei D. Wang , Anantha K. Subramani , Jianming Fu , Praburam Gopalraja , Jick M. Yu , Fusen Chen
IPC分类号： H01L021/44 , C23C014/32
CPC分类号： C23C14/046 , C23C14/185 , C23C14/345 , C23C14/3492 , C23C14/541 , H01L21/2855 , H01L21/76844 , H01L21/76865 , H01L21/76877
摘要： A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100null C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200null C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.
摘要翻译：将铜填充到高纵横比或双镶嵌结构的两步法。第一步在不超过100℃的低温下进行喷射，并且至少部分高晶片偏置，从而填充孔的下半部分。初始铜溅射优选通过多个低水平和高水平基座偏压的周期进行，以在暴露的拐角上沉积铜，并且在沉积在孔中深处时从角部溅射所得到的突出端。第二步可以包括在较高温度例如至少200℃进行的电化学电镀或溅射，并且具有较低的晶片偏置以完成孔填充。在本发明的另一方面，将扩散促进气体如氢气加入到铜溅射等离子体中。

2. 发明申请

US20040152330A1 Tunneling barrier for a copper damascene via 审中-公开
标题翻译：铜大马士革通道的隧道屏障
公开(公告)号：US20040152330A1
公开(公告)日：2004-08-05
申请号：US10700325
申请日：2003-11-03
申请人： APPLIED MATERIALS, INC.
发明人： Jick M. Yu , Ling Chen
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/76843
摘要： A process of forming a via through a inter-level dielectric layer and the product. The via is formed by etching a via hole through the inter-level dielectric layer in an area overlying a conductive feature, such a lower copper metallization. Atomic layer deposition (ALD) forms a very thin refractory metal nitride barrier layer over the sidewalls and bottom of the via. Its thickness is less than 1.5 nm, and may be formed with no more than six ALD cycle. A copper seed layer is sputtered onto the barrier including the bottom portion, and copper is electrochemically filled into the hole. The barrier is thin enough to have a low electrical resistance, as may be explained by electronic quantum mechanical tunneling. Further, the crystallography and defects of the underlying copper continue across the thin barrier into the overlying copper.
摘要翻译：通过层间电介质层和产品形成通孔的工艺。通过在覆盖导电特征的区域（例如较低的铜金属化物）中蚀刻通过层间电介质层的通孔来形成通孔。原子层沉积（ALD）在通孔的侧壁和底部上形成非常薄的难熔金属氮化物阻挡层。其厚度小于1.5nm，并且可以形成不超过六个ALD循环。将铜种子层溅射到包括底部的阻挡层上，铜电化学填充到孔中。阻挡层足够薄以具有低电阻，如电子量子力学隧道法所解释的那样。此外，底层铜的晶体学和缺陷继续穿过薄屏障进入覆盖铜。

3. 发明申请

US20040055893A1 Wafer backside electrical contact for electrochemical deposition and electrochemical mechanical polishing 审中-公开
标题翻译：晶圆背面电接触用于电化学沉积和电化学机械抛光
公开(公告)号：US20040055893A1
公开(公告)日：2004-03-25
申请号：US10253240
申请日：2002-09-23
申请人： Applied Materials, Inc.
发明人： Dmitry Lubomirsky , Michael X. Yang , Sheshraj Tulshibagwale , Yezdi Dordi , Howard E. Grunes , Jick M. Yu , Fusen Chen
IPC分类号： C25D017/00 , C25D005/02
CPC分类号： C25D7/123 , C25D17/06 , H01L21/2885
摘要： A method and apparatus for electrochemically plating on a production surface of a substrate are provided. The apparatus generally includes a plating cell having a plating solution reservoir configured to contain a volume of an electrochemical plating solution, and a substrate support member positioned above the plating solution reservoir, the substrate support member being configured to electrically engage a non-production side of a substrate secured thereto. The substrate support member generally includes a substrate support surface having at least one vacuum channel formed therein, a plurality of electrical contact pins extending from the substrate support surface and being positioned to engage a perimeter of the non-production side of the substrate secured thereto, and at least one annular seal positioned on the substrate support surface radially outward of the plurality of electrical contact pins, the at least one annular seal being configured to prevent flow of the electrochemical plating solution to the plurality of electrical contact pins. The plating cell further includes a power supply in electrical communication with an anode positioned in the electrochemical plating solution and the plurality of electrical contact pins.
摘要翻译：提供了一种用于在基板的生产表面上进行电化学电镀的方法和装置。该装置通常包括具有电镀液储存器的电镀槽，该电镀液储存器构造为容纳一定量的电化学电镀溶液，以及位于电镀液储存器上方的基板支撑构件，该基板支撑构件被构造成电接合非电解镀层固定到其上的基板。衬底支撑构件通常包括具有形成在其中的至少一个真空通道的衬底支撑表面，从衬底支撑表面延伸并定位成接合固定到其上的衬底的非生产侧的周边的多个电接触销，以及至少一个环形密封件，其定位在所述多个电接触销的径向外侧的所述基板支撑表面上，所述至少一个环形密封件构造成防止所述电化学电镀液流向所述多个电接触销。电镀单元还包括与位于电化学电镀溶液中的阳极和多个电接触针电连通的电源。

4. 发明申请

US20030216037A1 Method and apparatus for sputter deposition 有权
标题翻译：用于溅射沉积的方法和装置
公开(公告)号：US20030216037A1
公开(公告)日：2003-11-20
申请号：US10409406
申请日：2003-04-07
申请人： Applied Materials, Inc.
发明人： Hong Zhang , Xianmin Tang , Praburam Gopalraja , John C. Forster , Jick M. Yu
IPC分类号： C23C014/00 , C23C014/32 , H01L021/4763
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/0641 , C23C14/185 , C23C14/5873 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76865
摘要： A first method is provided for forming a barrier layer on a substrate by sputter-depositing a tantalum nitride layer on a substrate having (1) a metal feature formed on the substrate; (2) a dielectric layer formed over the metal feature; and (3) a via formed in the dielectric layer so as to expose the metal feature. The via has side walls and a bottom, and a width of about 0.18 microns or less. The tantalum nitride layer is deposited on the side walls and bottom of the via and on a field region of the dielectric layer; and has a thickness of at least about 200 angstroms on the field region. The first method also includes sputter-depositing a tantalum layer on the substrate, in the same chamber. The tantalum layer having a thickness of less than about 100 angstroms on the field region. Other aspects are provided.
摘要翻译：提供了第一种方法，用于通过在（1）形成在基底上的金属特征的衬底上溅射沉积氮化钽层，在衬底上形成阻挡层; （2）形成在所述金属特征上的电介质层; 和（3）形成在电介质层中的通孔以暴露金属特征。通孔具有侧壁和底部，宽度为约0.18微米或更小。氮化钽层沉积在通孔的侧壁和底部以及电介质层的场区上; 并且在场区域具有至少约200埃的厚度。第一种方法还包括在相同的室中在衬底上溅射沉积钽层。该钽层的厚度在场区域上小于约100埃。提供其他方面。

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