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1. 发明授权

US06768142B2 Circuit component placement 失效
标题翻译：电路元件放置
公开(公告)号：US06768142B2
公开(公告)日：2004-07-27
申请号：US10140965
申请日：2002-05-08
申请人： Anwar Ali , Tauman T. Lau , Max M. Yeung , Ken Nguyen , Wei Huang
发明人： Anwar Ali , Tauman T. Lau , Max M. Yeung , Ken Nguyen , Wei Huang
IPC分类号： H01L2710
CPC分类号： H01L24/06 , H01L23/50 , H01L24/02 , H01L27/118 , H01L2224/05554 , H01L2224/05599 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/45099
摘要： A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs. In various preferred embodiments, the bonding pads for the input output cells are disposed within their surface areas, thereby further reducing the surface area of the integrated circuit that is required for the input output functions of the integrated circuit.
摘要翻译：一种用于设计集成电路的输入输出单元的方法。输入输出单元格具有所需的区域，宽度和高度。测量集成电路的相邻焊盘之间的焊盘间距长度。输入输出单元的宽度被规定为基本上等于接合垫间距长度。将所需区域除以宽度以确定第一值，并且将输入输出单元的高度指定为基本上等于第一值。以这种方式，输入输出单元的宽度不大于两个相邻键合焊盘之间的距离，因此输入输出单元可以非常靠近地放置在一起，便于它们在输入输出有限的集成电路设计中使用。然而，输入输出单元的高度不大于包围输入输出单元的所需面积所需的高度，因此有助于它们在核心有限集成电路设计中的使用。在各种优选实施例中，用于输入输出单元的接合焊盘设置在它们的表面区域内，从而进一步减小集成电路的输入输出功能所需的集成电路的表面积。

2. 发明授权

US06683476B2 Contact ring architecture 失效
标题翻译：联系环架构
公开(公告)号：US06683476B2
公开(公告)日：2004-01-27
申请号：US10140967
申请日：2002-05-08
申请人： Anwar Ali , Tauman T. Lau , Max M. Yeung
发明人： Anwar Ali , Tauman T. Lau , Max M. Yeung
IPC分类号： H01L2500
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
摘要翻译：具有布置在集成电路的第一层上的VDDio总线的集成电路。 VDDio总线沿着长度设置，并且具有横向于该长度的第一宽度。 VSSio总线布置在集成电路的第二层上。 VSSio总线沿着该长度设置并且具有横向于该长度的第二宽度。 VSSio总线的第二宽度基本上与VDDio总线的第一宽度重叠。输入输出单元设置在集成电路的第三层上。第一层，第二层和第三层都是集成电路的不同层。输入输出单元具有电连接到VDDio总线的第一晶体管和与VSSio总线电连接的第二晶体管。第一晶体管和第二晶体管沿着输入输出单元内的长度设置。

3. 发明授权

US06784102B2 Laterally interconnecting structures 有权
标题翻译：横向互连结构
公开(公告)号：US06784102B2
公开(公告)日：2004-08-31
申请号：US10267810
申请日：2002-10-09
申请人： Max M. Yeung , Tauman T. Lau , Anwar Ali
发明人： Max M. Yeung , Tauman T. Lau , Anwar Ali
IPC分类号： H01L2144
CPC分类号： H01L23/5283 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
摘要翻译：一种在集成电路中增加第一结构和第二相邻结构之间的机械互锁的方法。第一结构形成有具有第一水平分量的第一表面，并且第二结构形成有具有第二水平分量的第二表面。第一表面横向接合第二表面，第一水平部件与第二水平部件互补，使得第一结构禁止第二结构的垂直运动。

4. 发明授权

US06998638B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06998638B2
公开(公告)日：2006-02-14
申请号：US10856213
申请日：2004-05-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

5. 发明授权

US06798069B1 Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors 有权
标题翻译：集成电路具有适应性强的核心和输入/输出区域，具有多层焊盘跟踪导体
公开(公告)号：US06798069B1
公开(公告)日：2004-09-28
申请号：US10402054
申请日：2003-03-28
申请人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/50 , H01L24/45 , H01L24/49 , H01L2224/05554 , H01L2224/451 , H01L2224/4943 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.
摘要翻译：提供一种集成电路，其包括在第一，第二或第三排接合焊盘处。提供了多个迹线导体以将每个焊盘的信号路由到I / O环和/或核。不同金属宽度的迹线导体配置在单独和不同的金属层上，使得可以在焊盘行和其它迹线导体的上方或下方进行布线。提供多个通孔以连接不同的金属层。这允许将多排接合焊盘布置在芯的周边上，而不必对小间距距离或较长路由路径造成损害。

6. 发明授权

US07569472B2 Method and apparatus of power ring positioning to minimize crosstalk 有权
标题翻译：电源环定位的方法和设备，以减少串扰
公开(公告)号：US07569472B2
公开(公告)日：2009-08-04
申请号：US11590961
申请日：2006-10-31
申请人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
IPC分类号： H01L21/44
CPC分类号： H01L23/552 , H01L23/3128 , H01L23/49838 , H01L23/49861 , H01L23/50 , H01L23/585 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48233 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/4943 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
摘要翻译：公开了一种用于最小化串扰的功率环定位的方法和/或装置。在一个实施例中，一种方法包括在功率环和管芯之间产生指状物阵列，在管芯的接合焊盘和指状物阵列的特定手指之间施加信号线，以及在相邻接合点之间施加屏蔽线焊盘和电源环，使得屏蔽线比信号线长，并且不耦合到手指阵列中的任何一个。屏蔽线可以放置在信号线的相邻信号线之间，以使相邻的信号线之间的串扰最小化。

7. 发明授权

US07328417B2 Cell-based method for creating slotted metal in semiconductor designs 有权
标题翻译：用于在半导体设计中创建开槽金属的基于单元的方法
公开(公告)号：US07328417B2
公开(公告)日：2008-02-05
申请号：US10732395
申请日：2003-12-09
申请人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
IPC分类号： G06F9/45
CPC分类号： G06F17/5068 , H01L27/0203
摘要： A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.
摘要翻译：公开了一种用于在半导体设计中产生开槽金属结构的计算机实现的方法。本发明的方面包括提供不同类型的预开槽构件块元件的库。此后，在芯片设计期间，从库中选择多个元件并将其放置在邻接的设计中以形成复合开槽金属结构。

8. 发明授权

US07863716B2 Method and apparatus of power ring positioning to minimize crosstalk 有权
标题翻译：电源环定位的方法和设备，以减少串扰
公开(公告)号：US07863716B2
公开(公告)日：2011-01-04
申请号：US12507831
申请日：2009-07-23
申请人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T Lau , Kalyan Doddapaneni
IPC分类号： H01L23/495
CPC分类号： H01L23/552 , H01L23/3128 , H01L23/49838 , H01L23/49861 , H01L23/50 , H01L23/585 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48233 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/4943 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.
摘要翻译：公开了一种用于最小化串扰的功率环定位的方法和/或装置。在一个实施例中，一种方法包括在功率环和管芯之间产生指状物阵列，在管芯的接合焊盘和指状物阵列的特定手指之间施加信号线，以及在相邻接合点之间施加屏蔽线焊盘和电源环，使得屏蔽线比信号线长，并且不耦合到手指阵列中的任何一个。屏蔽线可以放置在信号线的相邻信号线之间，以使相邻的信号线之间的串扰最小化。

9. 发明授权

US07737564B2 Power configuration method for structured ASICs 有权
标题翻译：结构化ASIC的电源配置方法
公开(公告)号：US07737564B2
公开(公告)日：2010-06-15
申请号：US11334870
申请日：2006-01-19
申请人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman T. Lau , Kalyan Doddapaneni
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L24/17 , H01L24/49 , H01L27/11898 , H01L2224/0401 , H01L2224/04073 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/16 , H01L2224/49171 , H01L2224/4943 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.
摘要翻译：公开了一种用于将诸如现场可编程设备，专用集成电路或快速芯片的集成电路的接合焊盘电耦合到输入/输出设备的方法。接合焊盘设置有可配置用于与输入/输出设备连接的多个金属层。接合焊盘然后与互连结构耦合到输入/输出设备。将接合焊盘电耦合到输入/输出设备的方法允许客户在切片创建之后配置电源和接地焊盘计数。

10. 发明授权

US06781150B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06781150B2
公开(公告)日：2004-08-24
申请号：US10229601
申请日：2002-08-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L2358
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

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