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1. 发明授权

US06784102B2 Laterally interconnecting structures 有权
标题翻译：横向互连结构
公开(公告)号：US06784102B2
公开(公告)日：2004-08-31
申请号：US10267810
申请日：2002-10-09
申请人： Max M. Yeung , Tauman T. Lau , Anwar Ali
发明人： Max M. Yeung , Tauman T. Lau , Anwar Ali
IPC分类号： H01L2144
CPC分类号： H01L23/5283 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
摘要翻译：一种在集成电路中增加第一结构和第二相邻结构之间的机械互锁的方法。第一结构形成有具有第一水平分量的第一表面，并且第二结构形成有具有第二水平分量的第二表面。第一表面横向接合第二表面，第一水平部件与第二水平部件互补，使得第一结构禁止第二结构的垂直运动。

2. 发明授权

US07117420B1 Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories 有权
标题翻译：构建半导体存储器中软错误的优化SEC-DED代码和逻辑
公开(公告)号：US07117420B1
公开(公告)日：2006-10-03
申请号：US09975293
申请日：2001-10-11
申请人： Max M. Yeung , Richard J. Stephani , Miguel A. Vilchis
发明人： Max M. Yeung , Richard J. Stephani , Miguel A. Vilchis
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： H03M13/095
摘要： An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.
摘要翻译：一种用于存储器错误控制编码的装置，包括第一电路和第二电路。第一电路可以被配置为响应于读取数据信号和读取奇偶校验信号而产生多位数字校正信号。第二电路可以被配置为（i）当校正子信号的比特不是全部相同的状态时检测错误，并且（ii）响应于校正子信号产生错误定位信号。误差位置信号可以响应于校正子信号的少于全部比特而产生。

3. 发明授权

US06815812B2 Direct alignment of contacts 有权
标题翻译：直接对齐触点
公开(公告)号：US06815812B2
公开(公告)日：2004-11-09
申请号：US10141252
申请日：2002-05-08
申请人： Anwar Ali , Ken Nguyen , Max M. Yeung
发明人： Anwar Ali , Ken Nguyen , Max M. Yeung
IPC分类号： H05K706
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.

4. 发明授权

US06683476B2 Contact ring architecture 失效
标题翻译：联系环架构
公开(公告)号：US06683476B2
公开(公告)日：2004-01-27
申请号：US10140967
申请日：2002-05-08
申请人： Anwar Ali , Tauman T. Lau , Max M. Yeung
发明人： Anwar Ali , Tauman T. Lau , Max M. Yeung
IPC分类号： H01L2500
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.
摘要翻译：具有布置在集成电路的第一层上的VDDio总线的集成电路。 VDDio总线沿着长度设置，并且具有横向于该长度的第一宽度。 VSSio总线布置在集成电路的第二层上。 VSSio总线沿着该长度设置并且具有横向于该长度的第二宽度。 VSSio总线的第二宽度基本上与VDDio总线的第一宽度重叠。输入输出单元设置在集成电路的第三层上。第一层，第二层和第三层都是集成电路的不同层。输入输出单元具有电连接到VDDio总线的第一晶体管和与VSSio总线电连接的第二晶体管。第一晶体管和第二晶体管沿着输入输出单元内的长度设置。

5. 发明授权

US06768142B2 Circuit component placement 失效
标题翻译：电路元件放置
公开(公告)号：US06768142B2
公开(公告)日：2004-07-27
申请号：US10140965
申请日：2002-05-08
申请人： Anwar Ali , Tauman T. Lau , Max M. Yeung , Ken Nguyen , Wei Huang
发明人： Anwar Ali , Tauman T. Lau , Max M. Yeung , Ken Nguyen , Wei Huang
IPC分类号： H01L2710
CPC分类号： H01L24/06 , H01L23/50 , H01L24/02 , H01L27/118 , H01L2224/05554 , H01L2224/05599 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/45099
摘要： A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs. In various preferred embodiments, the bonding pads for the input output cells are disposed within their surface areas, thereby further reducing the surface area of the integrated circuit that is required for the input output functions of the integrated circuit.
摘要翻译：一种用于设计集成电路的输入输出单元的方法。输入输出单元格具有所需的区域，宽度和高度。测量集成电路的相邻焊盘之间的焊盘间距长度。输入输出单元的宽度被规定为基本上等于接合垫间距长度。将所需区域除以宽度以确定第一值，并且将输入输出单元的高度指定为基本上等于第一值。以这种方式，输入输出单元的宽度不大于两个相邻键合焊盘之间的距离，因此输入输出单元可以非常靠近地放置在一起，便于它们在输入输出有限的集成电路设计中使用。然而，输入输出单元的高度不大于包围输入输出单元的所需面积所需的高度，因此有助于它们在核心有限集成电路设计中的使用。在各种优选实施例中，用于输入输出单元的接合焊盘设置在它们的表面区域内，从而进一步减小集成电路的输入输出功能所需的集成电路的表面积。

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