专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070177702A1 Receiving data over channels with intersymbol interference 审中-公开
标题翻译：通过符号间干扰的信道接收数据
公开(公告)号：US20070177702A1
公开(公告)日：2007-08-02
申请号：US11338176
申请日：2006-01-23
申请人： Anthony Sanders , Matthias Schobinger , Edoardo Prete , Norbert Neurohr , Johannes Sturm , Eva Tatschl-Unterberger , Nicola Dadalt , Daniele Gardellini
发明人： Anthony Sanders , Matthias Schobinger , Edoardo Prete , Norbert Neurohr , Johannes Sturm , Eva Tatschl-Unterberger , Nicola Dadalt , Daniele Gardellini
IPC分类号： H03D3/24
CPC分类号： H04L7/0058
摘要： A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.
摘要翻译：一种接收数据的方法包括对数据采样点的数据进行采样，以获取与数据中包含的信息相对应的数据采样，并在数据采样点之间的中间采样点采样数据，以获得中间样本。取决于在至少一个中间采样点之前的数据采样点采样的先前数据采样点和在数据采样中采样的先前中间采样点之间的至少一个数据样本，在中间采样点的至少一个中间采样点处对数据进行校正在所述至少一个中间采样点之前。

2. 发明申请

US20080143386A1 CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE 有权
标题翻译：用于接收需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念
公开(公告)号：US20080143386A1
公开(公告)日：2008-06-19
申请号：US11641545
申请日：2006-12-19
申请人： Georg Braun , Dirk Scheideler , Steve Wood , Richard Johannes Luyken , Edoardo Prete , Hans-Peter Trost , Anthony Sanders
发明人： Georg Braun , Dirk Scheideler , Steve Wood , Richard Johannes Luyken , Edoardo Prete , Hans-Peter Trost , Anthony Sanders
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.
摘要翻译：使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压可控开关包括电阻元件或与电阻元件分离。接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

3. 发明授权

US07936201B2 Apparatus and method for providing a signal for transmission via a signal line 有权
标题翻译：用于提供用于经由信号线传输的信号的装置和方法
公开(公告)号：US07936201B2
公开(公告)日：2011-05-03
申请号：US11644998
申请日：2006-12-22
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F5/06
CPC分类号： G06F13/1668
摘要： An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.
摘要翻译：一种用于经由信号线提供用于传输的信号的装置包括控制器电路，其具有用于指示信号线是否将处于非活动状态的信号的输出和耦合到控制器电路的开关电路，并且具有耦合到信号线。如果信号指示信号线处于非活动状态，则输出在不同的信号电平之间切换。

4. 发明申请

US20080126816A1 Apparatus and method for switching an apparatus to a power saving mode 有权
标题翻译：一种用于将设备切换到省电模式的装置和方法
公开(公告)号：US20080126816A1
公开(公告)日：2008-05-29
申请号：US11604666
申请日：2006-11-27
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F13/1673 , G11C5/04 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.
摘要翻译：可以作为锁存级连接到异步锁存链中的装置包括接收接口，其中在接收接口处接收到第一信号时，装置切换到第一省电模式和第二省电模式之一，这取决于在所述接收接口处的所述第二信号，并且其中所述设备在所述第一省电模式中提供第一功率消耗和第一唤醒时间，以及在所述第二省电模式中提供第二功率消耗和第二唤醒时间。

5. 发明授权

US07420430B2 Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals 有权
标题翻译：用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置
公开(公告)号：US07420430B2
公开(公告)日：2008-09-02
申请号：US11194494
申请日：2005-08-01
申请人： Claudio Andreotti , Edoardo Prete , Anthony Sanders
发明人： Claudio Andreotti , Edoardo Prete , Anthony Sanders
IPC分类号： H03B28/00
CPC分类号： H03K5/13 , H03K2005/00286 , H04L7/0025
摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.
摘要翻译：用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

6. 发明申请

US20070183553A1 Clock and data recovery circuit having gain control 有权
标题翻译：时钟和数据恢复电路具有增益控制
公开(公告)号：US20070183553A1
公开(公告)日：2007-08-09
申请号：US11346905
申请日：2006-02-03
申请人： Anthony Sanders , Dirk Scheideler , Edoardo Prete
发明人： Anthony Sanders , Dirk Scheideler , Edoardo Prete
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/091 , H03L7/093
摘要： A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.
摘要翻译：时钟和数据恢复电路包括相位检测器，被配置为将数据信号的相位与采样时钟的相位进行比较以提供相位误差信号;增益级，被配置为对相位误差信号施加增益以提供放大相位误差信号，以及被配置为对放大的相位误差信号进行滤波以提供相位校正信号的滤波器。该电路包括：增益控制器，被配置为响应于相位校正信号调整增益级的增益;以及时钟发生器，被配置为基于相位校正信号提供采样时钟。

7. 发明申请

US20060029172A1 Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals 有权
标题翻译：用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置
公开(公告)号：US20060029172A1
公开(公告)日：2006-02-09
申请号：US11194494
申请日：2005-08-01
申请人： Claudio Andreotti , Edoardo Prete , Anthony Sanders
发明人： Claudio Andreotti , Edoardo Prete , Anthony Sanders
IPC分类号： H04L7/00
CPC分类号： H03K5/13 , H03K2005/00286 , H04L7/0025
摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.
摘要翻译：用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

8. 发明授权

US07782927B2 Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator 有权
标题翻译：使用振荡器产生收发器的传输时钟信号和接收时钟信号
公开(公告)号：US07782927B2
公开(公告)日：2010-08-24
申请号：US10991671
申请日：2004-11-18
申请人： Philipp Börker , Bruno Celli-Urbani , Dirk Friebe , David Müller , Edoardo Prete , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
发明人： Philipp Börker , Bruno Celli-Urbani , Dirk Friebe , David Müller , Edoardo Prete , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
IPC分类号： H04B1/38 , H04L5/16 , H03D3/24 , H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/23 , H03L7/07 , H03L7/0814 , H03L7/095 , H03L2207/06 , H04L7/033
摘要： An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.
摘要翻译：提出了一种用于产生传输时钟信号和接收时钟信号的装置，其中仅使用单个压控振荡器，接收时钟信号由相位调节装置产生，而传输时钟信号由电压 - 受控振荡器。可以以这种方式防止多个压控振荡器之间的串扰。此外，提出了优化这种电路的各种措施。

9. 发明授权

US07532695B2 Clock signal extraction device and method for extracting a clock signal from data signal 有权
标题翻译：时钟信号提取装置和从数据信号提取时钟信号的方法
公开(公告)号：US07532695B2
公开(公告)日：2009-05-12
申请号：US10530852
申请日：2002-10-10
申请人： Anthony Sanders , Edoardo Prete
发明人： Anthony Sanders , Edoardo Prete
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/07 , H03L7/091 , H04L7/033
摘要： A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal. The device also includes a clock generator for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. A method for extracting a clock signal from a periodic data signal is related to the device.
摘要翻译：一种用于从周期性数据信号中提取时钟信号的时钟信号提取装置包括相位检测器，用于检测所述数据信号的上升沿与上升沿时钟信号之间的第一相位差，并且用于检测所述数据信号的下降沿之间的第二相位差数据信号和下降沿时钟信号。该装置还包括时钟发生器，用于产生所述上升沿时钟信号，使得所述第一相位差被最小化，用于产生所述下降沿时钟信号，使得所述第二相位差最小化，并且用于根据所述第一相位差产生所述时钟信号相位差和所述第二相位差。从周期性数据信号中提取时钟信号的方法与该装置有关。

10. 发明申请

US20080155150A1 Apparatus and method for providing a signal for transmission via a signal line 有权
标题翻译：用于提供用于经由信号线传输的信号的装置和方法
公开(公告)号：US20080155150A1
公开(公告)日：2008-06-26
申请号：US11644998
申请日：2006-12-22
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F13/00
CPC分类号： G06F13/1668
摘要： An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.
摘要翻译：一种用于经由信号线提供用于传输的信号的装置包括控制器电路，其具有用于指示信号线是否将处于非活动状态的信号的输出和耦合到控制器电路的开关电路，并且具有耦合到信号线。如果信号指示信号线处于非活动状态，则输出在不同的信号电平之间切换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式