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1. 发明申请

US20090072812A1 Event-Driven Time-Interval Measurement 有权
标题翻译：事件驱动的时间间隔测量
公开(公告)号：US20090072812A1
公开(公告)日：2009-03-19
申请号：US11855415
申请日：2007-09-14
申请人： Stephan Henzler , Matthias Schobinger
发明人： Stephan Henzler , Matthias Schobinger
IPC分类号： G01R13/02
CPC分类号： G04F10/00 , G04F10/005
摘要： An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.
摘要翻译：一种装置，包括被配置为仅参照包含在信号本身中的定时信息来测量第一信号中的特征之间的定时的电路。

2. 发明授权

US06069498A Clock generator for CMOS circuits with dynamic registers 失效
标题翻译：具有动态寄存器的CMOS电路的时钟发生器
公开(公告)号：US06069498A
公开(公告)日：2000-05-30
申请号：US945725
申请日：1997-11-05
申请人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
发明人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
IPC分类号： G06F1/04 , G11C7/22 , H03K5/151 , H03K5/153 , H03K5/19 , H03K9/06
CPC分类号： H03K5/153 , G11C7/22 , H03K5/19
摘要： An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.
摘要翻译： PCT No.PCT / DE96 / 00794 Sec。 371日期：1997年11月5日 102（e）日期1997年11月5日PCT提交1996年5月7日PCT公布。 WO96 / 36113 PCT出版物日期：1996年11月14日装置具有时钟监视装置，其确定输入时钟信号（PHI 0）的时钟速率是否已经低于预定的最小时钟速率。提供了一种系统，其从输入时钟信号形成主时钟信号（PHI m）和从时钟信号（PHI s），其形式使得动态主机寄存器（ML）的两个开关（S1）并且动态从属寄存器（SL）的开关（S2）关闭，只要时钟速率已经低于最小时钟速率。否则，动态从动锁存器（SL）的动态主锁存器（ML）或开关（S2）中的至少一个开关（S1）关闭。所实现的主要优点是，在输入时钟信号失效的情况下，特别是在具有高流水线流量的电路中，未定义的寄存器状态不会导致不允许的高电流消耗。

3. 发明申请

US20110109489A1 Data Converter Having a Passive Filter 有权
标题翻译：具有无源滤波器的数据转换器
公开(公告)号：US20110109489A1
公开(公告)日：2011-05-12
申请号：US12615994
申请日：2009-11-10
申请人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
发明人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
IPC分类号： H03M3/00 , H03M1/12 , H03M1/50
CPC分类号： H03M1/125 , H03M1/504
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译：公开了电路和系统的示例性实现方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。

4. 发明授权

US07804290B2 Event-driven time-interval measurement 有权
标题翻译：事件驱动的时间间隔测量
公开(公告)号：US07804290B2
公开(公告)日：2010-09-28
申请号：US11855415
申请日：2007-09-14
申请人： Stephan Henzler , Matthias Schobinger
发明人： Stephan Henzler , Matthias Schobinger
IPC分类号： G01R13/02 , G01R19/00
CPC分类号： G04F10/00 , G04F10/005
摘要： An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.
摘要翻译：一种装置，包括被配置为仅参照包含在信号本身中的定时信息来测量第一信号中的特征之间的定时的电路。

5. 发明授权

US08018366B2 Data converter having a passive filter 有权
标题翻译：数据转换器具有无源滤波器
公开(公告)号：US08018366B2
公开(公告)日：2011-09-13
申请号：US12615994
申请日：2009-11-10
申请人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
发明人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
IPC分类号： H03M1/12
CPC分类号： H03M1/125 , H03M1/504
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).
摘要翻译：公开了电路和系统的示例性实施方式，以及用于信号处理的方法，包括通过无源脉冲调制模数转换器（PMADC）实现的振幅和频带限制信号的采样和量化。

6. 发明申请

US20060198478A1 Method and apparatus for determining an output sequence from an input sequence 有权
公开(公告)号：US20060198478A1
公开(公告)日：2006-09-07
申请号：US11361666
申请日：2006-02-24
申请人： Norbert Neurohr , Matthias Schobinger
发明人： Norbert Neurohr , Matthias Schobinger
IPC分类号： H04B1/10
CPC分类号： H04L25/03057 , H04L2025/03496
摘要： A method and a device for determining an output sequence of output elements from an input sequence of input elements is provided, the method or the device being implemented according to a decision feedback equalizer. The adaptation of coefficients of the equalizer is performed on the basis of an estimated error determined as a function of a scaling (a, c0). According to the invention the scaling (a, c0) is determined such that it differs from a nominal input value by a deviation value during transmission without symbol interference. The deviation value is dependent on non-compensatable inter-symbol interference.

7. 发明授权

US5805239A Processor for comparing picture element blocks (blocks matching processor) 失效
标题翻译：用于比较像素块的处理器（块匹配处理器）
公开(公告)号：US5805239A
公开(公告)日：1998-09-08
申请号：US619637
申请日：1996-03-27
申请人： Luc De Vos , Matthias Schobinger
发明人： Luc De Vos , Matthias Schobinger
IPC分类号： G06T7/20 , H04N19/43 , H04N19/533 , H04N7/36
CPC分类号： G06T7/202 , H04N19/43 , H04N19/533
摘要： A processor is disclosed, in which a block memory (ADM), a search domain memory (SDM), a two-dimensional processor/memory cell field (PRA) and a control unit (CTRL) are preferably monolithically integrated in a semiconductor chip. The word width of toe search domain memory (SDM) is organised so that the processor/register cell field (PRA) is supplied, in parallel per system cycle (CLK) with data (SF) on picture elements of a new complete column of the search domain. At the same time, a control sequence is stored in the control unit (CTRL). The control sequence supplies data flow control signals (DFC) and addresses (ADR1, ADR2) to the block memory and search domain memory in parallel, per system cycle. The control unit essentially consists of a shift register into which external control signals (CD) of any desired control sequences may be written. An essential advantage of the invention is that it allows a comparatively high hardware utilisation even in the case of block matching algorithms based on an incomplete search.
摘要翻译： PCT No.PCT / DE94 / 01113 Sec。 371日期：1996年3月27日 102（e）1996年3月27日PCT 1994年9月23日PCT公布。公开号WO95 / 09404 日期1995年04月6日公开了一种处理器，其中块存储器（ADM），搜索域存储器（SDM），二维处理器/存储单元场（PRA）和控制单元（CTRL）优选地是单片集成在半导体芯片中。组织脚趾搜索域内存（SDM）的单词宽度，以便在每个系统周期（CLK）并行提供处理器/寄存器单元字段（PRA），其中数据（SF）在新的完整列的图像元素上搜索域。同时，控制序列存储在控制单元（CTRL）中。每个系统循环，控制顺序将数据流控制信号（DFC）和地址（ADR1，ADR2）并行提供给块存储器和搜索域存储器。控制单元基本上由移位寄存器组成，可以写入任何所需控制序列的外部控制信号（CD）。本发明的一个基本优点在于即使在基于不完全搜索的块匹配算法的情况下也允许相对较高的硬件利用率。

8. 发明申请

US20110279296A1 Data Converter Having a Passive Filter 有权
公开(公告)号：US20110279296A1
公开(公告)日：2011-11-17
申请号：US13187975
申请日：2011-07-21
申请人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
发明人： Stephan Henzler , Matthias Schobinger , Lajos Gazsi
IPC分类号： H03M1/12
CPC分类号： H03M1/125 , H03M1/504
摘要： Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

9. 发明申请

US20070177702A1 Receiving data over channels with intersymbol interference 审中-公开
标题翻译：通过符号间干扰的信道接收数据
公开(公告)号：US20070177702A1
公开(公告)日：2007-08-02
申请号：US11338176
申请日：2006-01-23
申请人： Anthony Sanders , Matthias Schobinger , Edoardo Prete , Norbert Neurohr , Johannes Sturm , Eva Tatschl-Unterberger , Nicola Dadalt , Daniele Gardellini
发明人： Anthony Sanders , Matthias Schobinger , Edoardo Prete , Norbert Neurohr , Johannes Sturm , Eva Tatschl-Unterberger , Nicola Dadalt , Daniele Gardellini
IPC分类号： H03D3/24
CPC分类号： H04L7/0058
摘要： A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.
摘要翻译：一种接收数据的方法包括对数据采样点的数据进行采样，以获取与数据中包含的信息相对应的数据采样，并在数据采样点之间的中间采样点采样数据，以获得中间样本。取决于在至少一个中间采样点之前的数据采样点采样的先前数据采样点和在数据采样中采样的先前中间采样点之间的至少一个数据样本，在中间采样点的至少一个中间采样点处对数据进行校正在所述至少一个中间采样点之前。

10. 发明申请

US20070038876A1 Circuit arrangement for activating a circuit block and method for the same 有权
标题翻译：用于激活电路块的电路布置及其方法
公开(公告)号：US20070038876A1
公开(公告)日：2007-02-15
申请号：US11454302
申请日：2006-06-15
申请人： Jorg Berthold , Geor Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
发明人： Jorg Berthold , Geor Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.
摘要翻译：集成电路包括功能块，控制向集成电路的不同功能块提供电力的功率控制单元，检测关闭功能块是否被接通的检测单元，以及控制该功能块的时钟信号控制单元提供功能块的时钟信号。时钟信号控制单元在预定数量的时钟周期中断集成电路的激活功能块的时钟信号。电源控制单元在中断的时钟周期期间向关闭的功能块供电。

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