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1. 发明申请

US20050068063A1 Differential to single-ended logic converter 失效
公开(公告)号：US20050068063A1
公开(公告)日：2005-03-31
申请号：US10672393
申请日：2003-09-25
申请人： David Muller , Volkmar Rebmann
发明人： David Muller , Volkmar Rebmann
IPC分类号： H03K5/003 , H03K5/24 , H03K19/0185 , H03K19/094
CPC分类号： H03K5/2481 , H03K5/003 , H03K19/018528
摘要： The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.

2. 发明授权

US06657479B2 Configuration having a current source and a switch connected in series therewith 有权
标题翻译：具有电流源和与其串联连接的开关的配置
公开(公告)号：US06657479B2
公开(公告)日：2003-12-02
申请号：US09972325
申请日：2001-10-05
申请人： Volkmar Rebmann
发明人： Volkmar Rebmann
IPC分类号： G05F110
CPC分类号： G05F3/242
摘要： The configuration described is distinguished by the fact that it contains a control device which ensures that the potential which is established on the current-source side terminal of the switch when the latter is open has the value which it would have if the switch were to be closed, under otherwise unchanged conditions, and if the current output by the current source were to flow through said switch. As a result, it is possible for the current output by the configuration always to be as large as desired, in particular even immediately directly after the closure of the switches P2 and N1, more precisely exactly the current output by the current sources P1 and N2.
摘要翻译：所描述的配置的区别在于它包含一个控制装置，该控制装置确保当开关的电流源侧端子上建立的电位在开关的电流源侧端子时具有如果开关将成为它将具有的值关闭，在其他不变的条件下，以及当前源的当前输出是否流过所述开关。结果，通过该配置的电流输出总是能够如所期望的那样大，特别是即使直接在开关P2和N1闭合之后，更准确地说，电流源P1和N2的电流输出。

3. 发明授权

US07782927B2 Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator 有权
标题翻译：使用振荡器产生收发器的传输时钟信号和接收时钟信号
公开(公告)号：US07782927B2
公开(公告)日：2010-08-24
申请号：US10991671
申请日：2004-11-18
申请人： Philipp Börker , Bruno Celli-Urbani , Dirk Friebe , David Müller , Edoardo Prete , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
发明人： Philipp Börker , Bruno Celli-Urbani , Dirk Friebe , David Müller , Edoardo Prete , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
IPC分类号： H04B1/38 , H04L5/16 , H03D3/24 , H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03L7/23 , H03L7/07 , H03L7/0814 , H03L7/095 , H03L2207/06 , H04L7/033
摘要： An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.
摘要翻译：提出了一种用于产生传输时钟信号和接收时钟信号的装置，其中仅使用单个压控振荡器，接收时钟信号由相位调节装置产生，而传输时钟信号由电压 - 受控振荡器。可以以这种方式防止多个压控振荡器之间的串扰。此外，提出了优化这种电路的各种措施。

4. 发明授权

US06924668B2 Differential to single-ended logic converter 失效
标题翻译：差分到单端逻辑转换器
公开(公告)号：US06924668B2
公开(公告)日：2005-08-02
申请号：US10672393
申请日：2003-09-25
申请人： David Müller , Volkmar Rebmann
发明人： David Müller , Volkmar Rebmann
IPC分类号： H03K5/003 , H03K5/24 , H03K19/0185 , H03K19/0175
CPC分类号： H03K5/2481 , H03K5/003 , H03K19/018528
摘要： The present invention is a converter stage for converting a differential logic input signal and a corresponding common mode differential logic signal each having a first single-ended logic signal and a complementary second single-ended logic signal into a single-ended logic output signal. The converter stage comprises a first and a second differential stage each having a first and a second MOS transistor and a first and second current source for the differential stages. According to the invention the current sources are controlled by the voltage level which is centered between the mid-potentials of the common mode level differential logic signal and the mid-potential of the differential logic input signal.
摘要翻译：本发明是一种用于将差分逻辑输入信号和各自具有第一单端逻辑信号和互补第二单端逻辑信号的相应共模差分逻辑信号转换为单端逻辑输出信号的转换器级。转换器级包括第一和第二差分级，每个具有第一和第二MOS晶体管以及用于差分级的第一和第二电流源。根据本发明，电流源由以共模电平差分逻辑信号的中间电位和差分逻辑输入信号的中间电位为中心的电压电平来控制。

5. 发明申请

US20050129099A1 Arrangement for generating a transmission clock signal and a reception clock signal for a transceiver 有权
标题翻译：用于产生收发机的传输时钟信号和接收时钟信号的装置
公开(公告)号：US20050129099A1
公开(公告)日：2005-06-16
申请号：US10991671
申请日：2004-11-18
申请人： Philipp Borker , Bruno Celli-Urbani , Dirk Friebe , David Muller , Edoardo Prette , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
发明人： Philipp Borker , Bruno Celli-Urbani , Dirk Friebe , David Muller , Edoardo Prette , Volkmar Rebmann , Anthony Sanders , Dirk Scheideler
IPC分类号： H03L7/07 , H03L7/081 , H03L7/095 , H03L7/23 , H04L7/033 , H04B1/38
CPC分类号： H03L7/23 , H03L7/07 , H03L7/0814 , H03L7/095 , H03L2207/06 , H04L7/033
摘要： An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.
摘要翻译：提出了一种用于产生传输时钟信号和接收时钟信号的装置，其中仅使用单个压控振荡器，接收时钟信号由相位调节装置产生，而传输时钟信号由电压 - 受控振荡器。可以以这种方式防止多个压控振荡器之间的串扰。此外，提出了优化这种电路的各种措施。

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