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1. 发明授权

US06538522B1 Method and ring oscillator for evaluating dynamic circuits 有权
标题翻译：用于评估动态电路的方法和环形振荡器
公开(公告)号：US06538522B1
公开(公告)日：2003-03-25
申请号：US09977423
申请日：2001-10-15
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger , David Michael Friend , Nghia Van Phan
IPC分类号： H03B2700
CPC分类号： H03K3/0315
摘要： Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit. The multiplexer receives the pulse output of the one-shot pulse generator and includes a select input for selecting the output of the dynamic circuit to be evaluated or the pulse output of the one-shot pulse generator. By inserting the evaluation circuit into a path that can be multiplexed in and out of the oscillator path, and by measuring the difference between the frequency with and without the evaluation circuit in the path, the performance of the evaluation circuit can be accurately determined.
摘要翻译：提供测量方法和环形振荡器电路用于评估动态电路。环形振荡器电路包括接收单个转换输入信号的单触发脉冲发生器，并产生具有上升的转换和下降转换的脉冲输出信号。要评估的动态电路耦合到接收单触发脉冲发生器的脉冲输出信号的单触发脉冲发生器的输出，并在输出端产生延迟的输出脉冲。二分之一电路耦合到待评估的动态电路的输出。二分之一电路的输出信号反馈给单触发脉冲发生器，重复循环，从而振荡。多路复用器连接在待评估的动态电路的输出端与分频电路之间。复用器接收单触发脉冲发生器的脉冲输出，并且包括用于选择要评估的动态电路的输出或单触发脉冲发生器的脉冲输出的选择输入。通过将评估电路插入到可以复用在振荡器路径中的路径之外，并且通过测量路径中具有和不具有评估电路的频率之间的差异，可以准确地确定评估电路的性能。

2. 发明授权

US5778243A Multi-threaded cell for a memory 失效
标题翻译：用于内存的多线程单元
公开(公告)号：US5778243A
公开(公告)日：1998-07-07
申请号：US675315
申请日：1996-07-03
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
IPC分类号： G06F12/00 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G11C8/16 , G06F12/02 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/3851 , G11C8/16
摘要： A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.
摘要翻译：一种用于多线程计算机系统中的多线程存储器（和相关方法），其中多个线程与单个处理器一起使用。多线程内存包括：多线程存储单元; 至少一个写入解码器，向所选择的多线程存储单元提供信息; 以及至少一个读取解码器从所选择的多线程存储单元访问信息。每个多线程存储单元包括：N个存储元件，其中N≥2，N个存储元件中的每一个具有线程通信内容; 写入接口，向所述小区内存储元件提供信息; 以及从单元内存储元件读取信息的读取接口。至少一个小区内读取和写入接口至少部分地通过识别对应的线程来选择线程对应内容之一，以实现小区内线程通信的内容选择。

3. 发明授权

US06901003B2 Lower power and reduced device split local and continuous bitline for domino read SRAMs 有权
标题翻译：降低功耗和减少器件分割本地和连续位线用于多米诺式读取SRAM
公开(公告)号：US06901003B2
公开(公告)日：2005-05-31
申请号：US10616847
申请日：2003-07-10
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
IPC分类号： G11C7/18 , G11C11/419 , G11C11/00
CPC分类号： G11C7/18 , G11C11/419
摘要： A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.
摘要翻译：提供了一种方法，装置和计算机程序来从SRAM单元读取标记。在写真线上生成一个低值。在连续的位线上生成高值。通过使用耦合到SRAM单元的真实节点的浮动电压来评估SRAM单元的真实节点。如果浮置电压保持大致恒定，则从SRAM单元读取的值为高。如果浮置电压耗尽地，则从SRAM单元读取的值为低电平。

4. 发明授权

US06657886B1 Split local and continuous bitline for fast domino read SRAM 有权
标题翻译：分割本地和连续的位线快速多米诺骨牌SRAM
公开(公告)号：US06657886B1
公开(公告)日：2003-12-02
申请号：US10140549
申请日：2002-05-07
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Todd Alan Christensen , Peter Thomas Freiburger
IPC分类号： G11C1140
CPC分类号： G11C11/419
摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.
摘要翻译：提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。多米诺SRAM包括多个本地小区组。多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。要写入SRAM单元补码节点，只需要驱动连续的补码位线。与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。

5. 发明授权

US06247166B1 Method and apparatus for assembling array and datapath macros 失效
标题翻译：阵列和数据路径宏的组合方法和装置
公开(公告)号：US06247166B1
公开(公告)日：2001-06-12
申请号：US09104621
申请日：1998-06-25
申请人： Anthony Gus Aipperspach , Peter Thomas Freiburger
发明人： Anthony Gus Aipperspach , Peter Thomas Freiburger
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method, computer program product and apparatus for assembling array and datapath macros are provided for very large scale integrated (VLSI) semiconductor integrated circuits. User selections are received for a hierarchical macro to be created. The user selections include a command list of multiple leaf cell build commands. X and Y placer pointers are initialized. A next build command is obtained from the command list and a command type is identified. Responsive to identifying a next leaf cell build command in a leaf cell group, a user selected schematic or physical view is identified. A corresponding leaf cell view is read for the user selected schematic or physical view. X and Y sizes are obtained for the leaf cell view. Then the leaf cell is oriented and placed. Next X and Y placer pointers are calculated and the sequential steps are repeated until a last leaf cell build command in the leaf cell group is found. Then the sequential steps return to obtain a next build command from the command list. Connections to adjacent leaf cells are provided by abutting cells together. Port and pin connections from the periphery of the array of placed leaf cells are propagated to a next hierarchical level of the hierarchical macro being created.
摘要翻译：为大规模集成（VLSI）半导体集成电路提供了一种用于组装阵列和数据路径宏的计算机程序产品和设备。接收到要创建的分层宏的用户选择。用户选择包括多个叶单元构建命令的命令列表。 X和Y指针被初始化。从命令列表中获取下一个构建命令，并识别命令类型。响应于在叶单元组中识别下一个叶细胞构建命令，识别用户选择的示意图或物理视图。为用户选择的原理图或物理视图读取相应的叶单元格视图。获得叶单元格视图的X和Y尺寸。然后叶细胞被定向和放置。计算下一个X和Y填充指针，并重复顺序步骤，直到找到叶细胞组中的最后一个叶细胞构建命令。然后，顺序步骤返回以从命令列表中获取下一个构建命令。通过邻接的细胞在一起提供与相邻叶细胞的连接。从放置的叶单元阵列的外围的端口和引脚连接被传播到正在创建的分层宏的下一层级。

6. 发明授权

US5835502A Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme 失效
标题翻译：用于处理串行共享静态方案中可变数据字宽和阵列深度的方法和装置
公开(公告)号：US5835502A
公开(公告)日：1998-11-10
申请号：US673258
申请日：1996-06-28
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
IPC分类号： G06F12/16 , G06F11/22 , G11C29/02 , G11C29/12 , G11C29/32 , G06F11/00
CPC分类号： G11C29/32
摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.
摘要翻译：一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。每个阵列包括预定的行和列地址深度和数据字宽度。每个阵列还包括扫描寄存器。生成通用测试数据字并将其发送到每个阵列的扫描寄存器。通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

7. 发明授权

US06509236B1 Laser fuseblow protection method for silicon on insulator (SOI) transistors 失效
公开(公告)号：US06509236B1
公开(公告)日：2003-01-21
申请号：US09588247
申请日：2000-06-06
申请人： Anthony Gus Aipperspach , Todd Alan Christensen
发明人： Anthony Gus Aipperspach , Todd Alan Christensen
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L27/0255 , H01L27/1203 , H01L2924/0002 , H03K17/08122 , H03K17/08142 , H01L2924/00
摘要： A method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground. A pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.

8. 发明授权

US07161390B2 Dynamic latching logic structure with static interfaces for implementing improved data setup time 失效
标题翻译：具有静态接口的动态锁存逻辑结构，用于实现改进的数据建立时间
公开(公告)号：US07161390B2
公开(公告)日：2007-01-09
申请号：US10926897
申请日：2004-08-26
申请人： Anthony Gus Aipperspach , Peter Thomas Freiburger
发明人： Anthony Gus Aipperspach , Peter Thomas Freiburger
IPC分类号： H03K19/20 , H03K19/094 , H03K19/096 , H03K19/00
CPC分类号： H03K19/0963
摘要： A latching dynamic logic includes a dynamic logic gate, a static logic input interface, and a set-reset output latch. The dynamic logic gate receives a clock signal, a data signal, and a select signal output of the static logic input interface. The dynamic logic gate includes a dynamic node and a pulldown network coupled to the dynamic node. The pulldown network selectively discharges the dynamic node following a clock signal transition dependent on the data signal and the select signal output of the static logic input interface being active. The set-reset output latch is coupled to the dynamic node of the dynamic logic gate for providing an output signal.
摘要翻译：锁存动态逻辑包括动态逻辑门，静态逻辑输入接口和置位复位输出锁存器。动态逻辑门接收静态逻辑输入接口的时钟信号，数据信号和选择信号输出。动态逻辑门包括耦合到动态节点的动态节点和下拉网络。下拉网络根据数据信号的时钟信号转换和静态逻辑输入接口的选择信号输出有效地选择性地放电动态节点。设置复位输出锁存器耦合到动态逻辑门的动态节点，用于提供输出信号。

9. 发明授权

US5991224A Global wire management apparatus and method for a multiple-port random access memory 失效
标题翻译：用于多端口随机存取存储器的全局线路管理装置和方法
公开(公告)号：US5991224A
公开(公告)日：1999-11-23
申请号：US84127
申请日：1998-05-22
申请人： Anthony Gus Aipperspach , Peter Thomas Freiburger , Peder James Paulson
发明人： Anthony Gus Aipperspach , Peter Thomas Freiburger , Peder James Paulson
IPC分类号： G11C8/14 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16 , G11C8/14
摘要： A global wire management apparatus and method for a multiple port random access memory (RAM) is disclosed. The RAM includes an array of stacked dual memory cell structures each including a common row/column decoder disposed between an upper memory cell and lower memory cell. The upper memory cell is situated adjacent upper transfer gate circuitry, and the lower memory cell is situated adjacent lower transfer gate circuitry. The decoder circuit is oriented vertically in the middle of the dual memory cell structure so that the true and complement decoder outputs may be fed upwards and downwards to the upper and lower transfer gate circuits. Wiring of the upper and lower transfer gate circuits may be effected completely at the local interconnect layer. Each of the write ports of the common decoder includes a NAND gate, an inverter, and a transfer gate for each of the upper and lower memory cells for controlling the transfer of data to the upper and lower memory cells. The disclosed global wiring management methodology provides an approach for reducing the number of global interconnect wires in a multiple port random access memory cell by sharing various wiring channels between memory cells. Such an approach allows a number of the memory cell global signal interconnects to be moved from the global wiring plane to the local wiring plane.
摘要翻译：公开了一种用于多端口随机存取存储器（RAM）的全局线管理装置和方法。 RAM包括堆叠的双存储器单元结构的阵列，每个阵列包括布置在上部存储器单元和下部存储器单元之间的公共行/列解码器。上存储器单元位于上传输门电路附近，并且下存储器单元位于下传输门电路附近。解码器电路在双存储单元结构的中间垂直取向，使得真和补码解码器输出可以向上和向下馈送到上传输门电路和下传输门电路。上部和下部传输门电路的接线可以在局部互连层完全实现。公共解码器的每个写入端口包括用于控制向上部和下部存储器单元传输数据的上部和下部存储器单元中的每一个的“与非”门，反相器和传输门。所公开的全局布线管理方法提供了一种通过在存储器单元之间共享各种布线通道来减少多端口随机存取存储单元中的全局互连线数量的方法。这种方法允许多个存储单元全局信号互连从全局布线平面移动到局部布线平面。

10. 发明授权

US06172531B2 Low power wordline decoder circuit with minimized hold time 失效
标题翻译：低功率字线解码电路，保持时间最短
公开(公告)号：US06172531B2
公开(公告)日：2001-01-09
申请号：US09251089
申请日：1999-02-16
申请人： Anthony Gus Aipperspach , Peter Thomas Freiburger
发明人： Anthony Gus Aipperspach , Peter Thomas Freiburger
IPC分类号： H03K190948
CPC分类号： G11C8/10 , G11C8/08 , H03K19/0963
摘要： A wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.
摘要翻译：提供了字线解码器电路和对字线输入信号进行解码的方法。第一解码器接收要评估的多个输入。第一解码器包括用于对第一节点进行预充电的第一预充电装置和用于使第一节点放电的第一放电装置。第一时钟信号使能第一放电装置。第一个时钟信号禁止预充电设备。时钟延迟电路接收第一时钟信号并产生延迟的时钟信号。第二逻辑耦合到第一解码器。第二个逻辑提供字线输出。第二逻辑字线输出响应于延迟的时钟信号被使能，并且响应于第一时钟信号被禁止。

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