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1. 发明授权

US5778243A Multi-threaded cell for a memory 失效
标题翻译：用于内存的多线程单元
公开(公告)号：US5778243A
公开(公告)日：1998-07-07
申请号：US675315
申请日：1996-07-03
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Binta Minesh Patel , Nghia Van Phan , Michael James Rohn , Salvatore Nicholas Storino , Bryan Joe Talik , Gregory John Uhlmann
IPC分类号： G06F12/00 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G11C8/16 , G06F12/02 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/3851 , G11C8/16
摘要： A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.
摘要翻译：一种用于多线程计算机系统中的多线程存储器（和相关方法），其中多个线程与单个处理器一起使用。多线程内存包括：多线程存储单元; 至少一个写入解码器，向所选择的多线程存储单元提供信息; 以及至少一个读取解码器从所选择的多线程存储单元访问信息。每个多线程存储单元包括：N个存储元件，其中N≥2，N个存储元件中的每一个具有线程通信内容; 写入接口，向所述小区内存储元件提供信息; 以及从单元内存储元件读取信息的读取接口。至少一个小区内读取和写入接口至少部分地通过识别对应的线程来选择线程对应内容之一，以实现小区内线程通信的内容选择。

2. 发明授权

US06305000B1 Placement of conductive stripes in electronic circuits to satisfy metal density requirements 有权
标题翻译：在电子电路中放置导电条以满足金属密度要求
公开(公告)号：US06305000B1
公开(公告)日：2001-10-16
申请号：US09334171
申请日：1999-06-15
申请人： Nghia Van Phan , Michael James Rohn
发明人： Nghia Van Phan , Michael James Rohn
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An electronic circuit and a method of designing the electronic circuit having conductive fill stripes which are electrically attached to the power distribution or to the signal routing of the circuit. Preferably, the conductive fill stripes are electrically attached to the power distribution and are interspersed between the power buses and signal wires on the various metal layers to satisfy the metal density requirements of integrated circuit and chip manufacturing. The conductive fill stripes are added during the design process after the placement of the power distribution and signal routing so that electrical continuity between the conductive fill stripes and the connecting bus, metal density requirements, other design rules and logic verification can be completed as the rest of the chip is designed.
摘要翻译：一种电子电路和一种设计具有导电填充条的电子电路的方法，所述导电填充条电连接到电力分配或电路的信号路由。优选地，导电填充条电连接到功率分布并且散布在各种金属层上的电源总线和信号线之间，以满足集成电路和芯片制造的金属密度要求。在布置配电和信号路由之后，在设计过程中添加导电填充条，使得导电填充条和连接总线之间的电连续性，金属密度要求，其他设计规则和逻辑验证可以作为其余部分完成的芯片设计。

3. 发明授权

US06909159B2 Method and apparatus to make a semiconductor chip susceptible to radiation failure 有权
标题翻译：使半导体芯片易受辐射破坏的方法和装置
公开(公告)号：US06909159B2
公开(公告)日：2005-06-21
申请号：US10176233
申请日：2002-06-20
申请人： David Michael Friend , Nghia Van Phan , Michael James Rohn
发明人： David Michael Friend , Nghia Van Phan , Michael James Rohn
IPC分类号： G11C11/412 , H01L21/762 , H01L27/12 , H03K19/173 , G11C5/00
CPC分类号： H03K19/1731 , G11C11/4125 , H01L21/76243 , H01L27/1203
摘要： Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.
摘要翻译：提供了用于降低半导体芯片的整体辐射硬度的方法和装置。提供了辐射检测器和故障存储器。故障存储器产生禁用信号或信号。禁用信号是用户逻辑功能的必需输入，例如片外驱动器，芯片外接收器，时钟或静态随机存取存储器。当辐射检测器检测到辐射时，该检测被存储在故障存储器中。禁用信号在有效时会导致部分或全部用户功能不起作用。当半导体芯片在绝缘体上绝缘体（SOI）互补金属氧化物半导体（CMOS）工艺制造时，本发明是特别重要的，其是自然辐射的。

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