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1. 发明授权

US06417096B1 Method for avoiding photo residue in dual damascene with acid treatment 有权
标题翻译：用酸处理避免双重镶嵌光斑残留的方法
公开(公告)号：US06417096B1
公开(公告)日：2002-07-09
申请号：US09611738
申请日：2000-07-07
申请人： Anseime Chen , Jun Maeda , Sheng-Yueh Chang , Sung-Hsiung Wang
发明人： Anseime Chen , Jun Maeda , Sheng-Yueh Chang , Sung-Hsiung Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76826 , H01L21/3105 , H01L21/31144 , H01L21/76807
摘要： A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.
摘要翻译：提供基板。通过沉积在衬底上形成第一介电层。蚀刻停止层和第二介电层依次形成在第一电介质上。接下来，第二介电层被处理路易斯酸。然后，在第二介电层上限定并形成第一光致抗蚀剂层。然后通过第一光致抗蚀剂层作为掩模进行干蚀刻以形成通孔。用路易斯酸处理第二介电层和通孔的表面。随后，第二光致抗蚀剂层被限定并形成在第二介电层上。进行干蚀刻，并且蚀刻停止层作为蚀刻终点以去除第二电介质层的暴露的部分表面，以形成具有比通孔更大的水平尺寸的沟槽。随后，去除第二光致抗蚀剂层以形成大马士革的开口。

2. 发明授权

US06583489B2 Method for forming interconnect structure with low dielectric constant 有权
公开(公告)号：US06583489B2
公开(公告)日：2003-06-24
申请号：US10103835
申请日：2002-03-25
申请人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
发明人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
IPC分类号： H01L2900
CPC分类号： H01L21/76802 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/318 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

3. 发明授权

US07297629B2 Ultra-thick metal-copper dual damascene process 有权
标题翻译：超厚金属铜双镶嵌工艺
公开(公告)号：US07297629B2
公开(公告)日：2007-11-20
申请号：US10942555
申请日：2004-09-15
申请人： Sung-Hsiung Wang
发明人： Sung-Hsiung Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76813 , H01L21/76816
摘要： Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.
摘要翻译：新型双镶嵌方法的特点是循环时间短，成本低。在一个实施例中，该方法包括在衬底上提供介电层; 蚀刻电介质层中的通孔; 用诸如铜的导电金属填充通孔; 在所述通孔上提供第二电介质层; 蚀刻第二介电层中的沟槽; 并用诸如铜的导电金属填充沟槽。在另一个实施例中，该方法包括在衬底上提供介电层; 蚀刻介电层中的部分通孔; 在部分通孔上蚀刻电介质层中的部分沟槽; 在单个蚀刻步骤中完成通孔和沟槽; 并用导电金属如铜填充通孔和沟槽，以分别完成通路和金属线。

4. 发明申请

US20060057842A1 Ultra-thick metal-copper dual damascene process 有权
标题翻译：超厚金属铜双镶嵌工艺
公开(公告)号：US20060057842A1
公开(公告)日：2006-03-16
申请号：US10942555
申请日：2004-09-15
申请人： Sung-Hsiung Wang
发明人： Sung-Hsiung Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76813 , H01L21/76816
摘要： Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.
摘要翻译：新型双镶嵌方法的特点是循环时间短，成本低。在一个实施例中，该方法包括在衬底上提供介电层; 蚀刻电介质层中的通孔; 用诸如铜的导电金属填充通孔; 在所述通孔上提供第二电介质层; 蚀刻第二介电层中的沟槽; 并用诸如铜的导电金属填充沟槽。在另一个实施例中，该方法包括在衬底上提供介电层; 蚀刻介电层中的部分通孔; 在部分通孔上蚀刻电介质层中的部分沟槽; 在单个蚀刻步骤中完成通孔和沟槽; 并用导电金属如铜填充通孔和沟槽，以分别完成通路和金属线。

5. 发明授权

US06903644B2 Inductor device having improved quality factor 有权
标题翻译：具有改善品质因数的电感器件
公开(公告)号：US06903644B2
公开(公告)日：2005-06-07
申请号：US10628150
申请日：2003-07-28
申请人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
发明人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
IPC分类号： H01F17/00 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0013 , H01F2017/008 , H01L2924/0002 , H01L2924/00
摘要： An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.
摘要翻译：一种包括第一线圈导体（310）和第二线圈导体（510）的电感器件，所述第一线圈导体（310）位于衬底（120）之上并且具有第一图案和第一导电性，并且所述第二线圈导体（510）位于所述第一线圈导体（310）的主要部分上，具有基本上符合所述第一图案的第二图案，并且具有基本上大于所述第一导电性的第二导电。

6. 发明申请

US20050024176A1 Inductor device having improved quality factor 有权
标题翻译：具有改善品质因数的电感器件
公开(公告)号：US20050024176A1
公开(公告)日：2005-02-03
申请号：US10628150
申请日：2003-07-28
申请人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
发明人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
IPC分类号： H01F17/00 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0013 , H01F2017/008 , H01L2924/0002 , H01L2924/00
摘要： An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.
摘要翻译：一种包括第一线圈导体（310）和第二线圈导体（510）的电感器件，所述第一线圈导体（310）位于衬底（120）之上并且具有第一图案和第一导电性，并且所述第二线圈导体（510）位于所述第一线圈导体（310）的主要部分上，具有基本上符合所述第一图案的第二图案，并且具有基本上大于所述第一导电性的第二导电。

7. 发明申请

US20080122029A1 Inductor utilizing pad metal layer 审中-公开
标题翻译：电感利用垫金属层
公开(公告)号：US20080122029A1
公开(公告)日：2008-05-29
申请号：US11592203
申请日：2006-11-03
申请人： Sung-Hsiung Wang , Chih-Ping Chao , Chia-Yi Su
发明人： Sung-Hsiung Wang , Chih-Ping Chao , Chia-Yi Su
IPC分类号： H01L29/00
CPC分类号： H01L28/10
摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.
摘要翻译：一种利用垫金属层的电感器。电感器包括金属螺旋，金属桥和金属互连。金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。金属互连连接到金属桥的另一端。此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

8. 发明授权

US06617234B2 Method of forming metal fuse and bonding pad 失效
标题翻译：形成金属熔丝和焊盘的方法
公开(公告)号：US06617234B2
公开(公告)日：2003-09-09
申请号：US09835014
申请日：2001-04-13
申请人： Sung-Hsiung Wang , Yimin Huang , Chiung-Sheng Hsiung
发明人： Sung-Hsiung Wang , Yimin Huang , Chiung-Sheng Hsiung
IPC分类号： H01L2144
CPC分类号： H01L24/02 , H01L23/5256 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , Y10S438/978
摘要： A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.
摘要翻译：一种形成金属熔断器和焊盘的方法。在衬底中形成导电层。介电层形成在衬底上。电介质层具有露出导电层的一部分的开口。在电介质层上形成金属层。将金属层图案化以形成金属熔丝和接合焊盘。接合焊盘经由开口电连接到导电层。金属保险丝和接合垫都有底切的侧壁。垫片形成在金属保险丝和接合垫的底切侧壁上。最后，在衬底上形成暴露金属熔丝和焊盘的钝化层。

9. 发明授权

US06355568B1 Cleaning method for copper dual damascene process 有权
标题翻译：铜双镶嵌工艺的清洗方法
公开(公告)号：US06355568B1
公开(公告)日：2002-03-12
申请号：US09580041
申请日：2000-05-26
申请人： Sung-Hsiung Wang , Chan-Lon Yang
发明人： Sung-Hsiung Wang , Chan-Lon Yang
IPC分类号： H01L21302
CPC分类号： H01L21/76814 , H01L21/02052 , H01L21/31116 , H01L21/76807 , H01L21/76838 , Y10S438/906
摘要： A cleaning method for a copper dual damascene process, applicable for cleaning a structure having a dual damascene opening. The method begins with preparing a first chemical solution and a second chemical solution. The first chemical solution includes a deionized water, a hydrogen peroxide, and a surfactant, whereas the second chemical solution includes a deionized water, a hydrogen fluoride, and a hydrogen chloride. A first cleaning step is performed using the first chemical solution to remove particles and polymers that remain on a surface of a copper layer and the dual damascene opening. This is followed by performing a second cleaning step using the second chemical solution to remove a copper oxide layer on the copper layer.
摘要翻译：铜双镶嵌工艺的清洁方法，适用于清洗具有双镶嵌开口的结构。该方法开始于制备第一种化学溶液和第二种化学溶液。第一种化学溶液包括去离子水，过氧化氢和表面活性剂，而第二种化学溶液包括去离子水，氟化氢和氯化氢。使用第一化学溶液进行第一清洗步骤以除去残留在铜层表面上的颗粒和聚合物以及双镶嵌开口。然后，使用第二化学溶液进行第二清洗步骤以除去铜层上的氧化铜层。

10. 发明授权

US07968968B2 Inductor utilizing pad metal layer 有权
标题翻译：电感利用垫金属层
公开(公告)号：US07968968B2
公开(公告)日：2011-06-28
申请号：US12790526
申请日：2010-05-28
申请人： Sung-Hsiung Wang , Chih-Ping Chao , Chia-Yu Su
发明人： Sung-Hsiung Wang , Chih-Ping Chao , Chia-Yu Su
IPC分类号： H01L27/08
CPC分类号： H01L28/10
摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.
摘要翻译：一种利用垫金属层的电感器。电感器包括金属螺旋，金属桥和金属互连。金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。金属互连连接到金属桥的另一端。此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

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