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1. 发明授权

US07265019B2 Elastomeric CMOS based micro electromechanical varactor 有权
标题翻译：弹性体CMOS微机电变容二极管
公开(公告)号：US07265019B2
公开(公告)日：2007-09-04
申请号：US10710286
申请日：2004-06-30
申请人： Anil K. Chinthakindi , Henri D. Schnurmann
发明人： Anil K. Chinthakindi , Henri D. Schnurmann
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01G5/18 , H01G5/38
摘要： A micro electro-mechanical system (MEMS) variable capacitor is described, wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate and are independently actuated. The electrodes are formed in an interdigitated fashion to maximize capacitance. The MEMS variable capacitor includes CMOS manufacturing steps in combination with elastomeric material selectively used in areas under greatest stress to ensure that the varactor will not fail as a result of stresses that may result in the separation of dielectric material from the conductive elements. The combination of a CMOS process with the conducting elastomeric material between vias increases the overall sidewall area, which provides increased capacitance density.
摘要翻译：描述了微机电系统（MEMS）可变电容器，其中相同极性的可移动梳状电极同时制造在相同的衬底上并且被独立地致动。电极以交叉形式形成以最大化电容。 MEMS可变电容器包括与在最大应力区域选择性地使用的弹性体材料组合的CMOS制造步骤，以确保变容二极管不会由于可能导致介电材料与导电元件分离的应力而失效。 CMOS工艺与通孔之间的导电弹性体材料的组合增加了整个侧壁面积，这提供了增加的电容密度。

2. 发明授权

US4811082A High performance integrated circuit packaging structure 失效
标题翻译：高性能集成电路封装结构
公开(公告)号：US4811082A
公开(公告)日：1989-03-07
申请号：US929946
申请日：1986-11-12
申请人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann
发明人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann
IPC分类号： H01L23/52 , H01L23/538 , H01L27/00 , H01L39/02 , H01L23/02 , H01L23/12
CPC分类号： H01L23/5383 , H01L23/538 , H01L2224/16225 , H01L2924/09701 , H01L2924/3011
摘要： A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.
摘要翻译：一种高速，高性能的集成电路封装结构，可用于仿真晶圆级整合结构。优选实施例包括具有基底基板的插入件，其上具有交替的绝缘层和导电层，其中多个导电层是用于在封装中保持极低噪声水平的布线装置。布线装置的低噪声电平和低电阻和电容允许多个分立的半导体段通过集成电路封装安装在其上并以与租赁规则要求相比大大减少的数量的驱动器和接收器相互连接。本发明的每个集成电路结构在性能上模拟大的芯片或晶片级整合结构，而不必产生大的芯片或晶片，并且没有冗余方案。多个这些集成电路封装结构通过贴花组合形成计算机或其一部分的中央处理单元。在替代的优选实施例中，插入器的基底衬底由硅制成，并且在其中形成任何所需的驱动器，从而基本上消除了对每个分立半导体段上的任何驱动器的需要。

3. 发明授权

US4866507A Module for packaging semiconductor integrated circuit chips on a base substrate 失效
标题翻译：在基板上封装半导体集成电路芯片的模块
公开(公告)号：US4866507A
公开(公告)日：1989-09-12
申请号：US864228
申请日：1986-05-19
申请人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： H01L23/12 , H01L23/50 , H01L23/538
CPC分类号： H01L23/5383 , H01L23/50 , H01L2224/16 , H01L2924/01014 , H01L2924/01079 , H01L2924/10253 , H01L2924/3011 , H01L2924/3025
摘要： An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card).The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.
摘要翻译：一种集成电路芯片封装结构，优选地具有半导体基底（即，硅或砷化镓），在基底结构上的交替绝缘和导电层，将至少两个导电层图案化成薄膜布线（即大约为薄膜铜 5微米），连接到最上层图案的导电层的半导体集成电路芯片，以及将封装结构连接到下一级封装（即板或卡）的装置。薄膜布线层通常各自具有共面的接地，功率和信号线，其中至少一个电源线或地线存在于共面信号线之间，以最小化串扰。为了便于有效的功率分配，图案化平面的特定功率电平的线被连接到在其它图案化平面上的相同功率电平的线以形成三维电源平面。为了减少封装电容并使RC恒定不变，引入了一个个性化的参考平面。个性化平面具有至少部分地延伸穿过平面的绝缘区域，该预定位置与布线层上的长信号线重合。组合封装提供具有优异的电性能（即，速度，低RC恒定，有效功率分布），下层半导体结构和安装在封装上的半导体芯片之间的高密度和热膨胀匹配的封装替代方案。还公开了用于制造封装的高产量工艺。

4. 发明授权

US4606025A Automatically testing a plurality of memory arrays on selected memory array testers 失效
标题翻译：自动测试选定的存储器阵列测试仪上的多个存储器阵列
公开(公告)号：US4606025A
公开(公告)日：1986-08-12
申请号：US536597
申请日：1983-09-28
申请人： Robert M. Peters , Henri D. Schnurmann , Louis J. Vidunas
发明人： Robert M. Peters , Henri D. Schnurmann , Louis J. Vidunas
IPC分类号： G11C29/00 , F02B75/02 , G01R31/28 , G01R31/319 , G06F11/22 , G11C29/54 , G11C29/56
CPC分类号： G11C29/56 , G11C29/54 , F02B2075/027 , G01R31/31908
摘要： A system for automatically testing a plurality of memory arrays on selected memory array testers includes an interactive data entry device for entering array test specifications including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator generates a tester independent universal language instruction sequence for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a universal language translator which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester. The tester dependent instruction sequence may be loaded into the associated tester to produce the test signals for testing the memory array.
摘要翻译：用于自动测试所选择的存储器阵列测试器上的多个存储器阵列的系统包括用于输入阵列测试规范的交互式数据输入设备，包括阵列的特征信息，DC测试参数，AC测试参数和AC测试模式选择。测试规格以与特定测试仪特性无关的格式输入。通用语言生成器生成测试仪独立的通用语言指令序列，用于根据输入的测试规范执行规定的测试。与每个测试器相关联的是通用语言翻译器，其将测试仪独立的通用语言指令序列转换成相关测试仪特有的指令序列。测试仪相关指令序列可以被加载到相关联的测试器中以产生用于测试存储器阵列的测试信号。

5. 发明授权

US4348759A Automatic testing of complex semiconductor components with test equipment having less channels than those required by the component under test 失效
标题翻译：使用测试设备的复杂半导体部件自动测试，通道数量小于被测部件所需的通道
公开(公告)号：US4348759A
公开(公告)日：1982-09-07
申请号：US104481
申请日：1979-12-17
申请人： Henri D. Schnurmann
发明人： Henri D. Schnurmann
IPC分类号： G01R31/28 , G01R31/319 , G06F11/12 , G01R15/12
CPC分类号： G01R31/31926
摘要： A method and apparatus for testing large or very large scale integrated circuit packages is described. The testing equipment required for testing such packages is assumed to lack the number of channels necessary to connect one channel to each input/output of the unit under test. A computer program classifies all input terminals in a plurality of categories, each of which corresponds to particular circuit type and electric network configuration connected to that pin. A unique set of DC levels is defined prior to testing for each class of inputs. These levels are supplied by the tester channels, each of which drives a multitude of input pins that belong to the same category. The assignment of tester channels in the aforementioned arrangement is implemented by means of multiplexers that select for each pin the appropriate set of DC levels, and a memory buffer contained in the tester, with the DC test patterns stored wherein. The bit configuration of each pattern controls plural switching devices that deliver the appropriate DC levels to the terminals of the unit.
摘要翻译：描述了用于测试大型或非常大规模集成电路封装的方法和装置。假设测试这种包装所需的测试设备缺少将一个通道连接到被测单元的每个输入/输出所需的通道数量。计算机程序将所有输入端子分类为多个类别，每个类别对应于连接到该引脚的特定电路类型和电网络配置。在测试每一类输入之前，定义了一组独特的DC级别。这些电平由测试仪通道提供，每个通道驱动属于同一类别的多个输入引脚。上述布置中的测试仪通道的分配通过多路复用器来实现，该多路复用器为每个引脚选择适当的DC电平集合，以及包含在测试器中的存储器缓冲器，其中存储有DC测试图案。每个模式的位配置控制将适当的DC电平递送到单元的端子的多个开关装置。

6. 发明授权

US4963824A Diagnostics of a board containing a plurality of hybrid electronic components 失效
标题翻译：包含多个混合电子部件的板的诊断
公开(公告)号：US4963824A
公开(公告)日：1990-10-16
申请号：US267409
申请日：1988-11-04
申请人： Edward P. Hsieh , Maurice T. McMahon , Henri D. Schnurmann
发明人： Edward P. Hsieh , Maurice T. McMahon , Henri D. Schnurmann
IPC分类号： G01R31/317 , G01R31/3185 , G06F11/26 , G06F11/273
CPC分类号： G06F11/261 , G01R31/318544 , G01R31/318566 , G06F11/2733
摘要： A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.

7. 发明授权

US4817093A Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure 失效
标题翻译：划分，测试和诊断VLSI多芯片封装及相关结构的方法
公开(公告)号：US4817093A
公开(公告)日：1989-03-28
申请号：US64976
申请日：1987-06-18
申请人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/27 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318385 , G06F11/27
摘要： A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

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