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1. 发明授权

US4817093A Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure 失效
标题翻译：划分，测试和诊断VLSI多芯片封装及相关结构的方法
公开(公告)号：US4817093A
公开(公告)日：1989-03-28
申请号：US64976
申请日：1987-06-18
申请人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Maurice T. McMahon, Jr. , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/27 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318385 , G06F11/27
摘要： A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

2. 发明授权

US4866507A Module for packaging semiconductor integrated circuit chips on a base substrate 失效
标题翻译：在基板上封装半导体集成电路芯片的模块
公开(公告)号：US4866507A
公开(公告)日：1989-09-12
申请号：US864228
申请日：1986-05-19
申请人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
发明人： Scott L. Jacobs , Perwaiz Nihal , Burhan Ozmat , Henri D. Schnurmann , Arthur R. Zingher
IPC分类号： H01L23/12 , H01L23/50 , H01L23/538
CPC分类号： H01L23/5383 , H01L23/50 , H01L2224/16 , H01L2924/01014 , H01L2924/01079 , H01L2924/10253 , H01L2924/3011 , H01L2924/3025
摘要： An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card).The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.
摘要翻译：一种集成电路芯片封装结构，优选地具有半导体基底（即，硅或砷化镓），在基底结构上的交替绝缘和导电层，将至少两个导电层图案化成薄膜布线（即大约为薄膜铜 5微米），连接到最上层图案的导电层的半导体集成电路芯片，以及将封装结构连接到下一级封装（即板或卡）的装置。薄膜布线层通常各自具有共面的接地，功率和信号线，其中至少一个电源线或地线存在于共面信号线之间，以最小化串扰。为了便于有效的功率分配，图案化平面的特定功率电平的线被连接到在其它图案化平面上的相同功率电平的线以形成三维电源平面。为了减少封装电容并使RC恒定不变，引入了一个个性化的参考平面。个性化平面具有至少部分地延伸穿过平面的绝缘区域，该预定位置与布线层上的长信号线重合。组合封装提供具有优异的电性能（即，速度，低RC恒定，有效功率分布），下层半导体结构和安装在封装上的半导体芯片之间的高密度和热膨胀匹配的封装替代方案。还公开了用于制造封装的高产量工艺。

3. 发明授权

US09748414B2 Self-activated front surface bias for a solar cell 有权
公开(公告)号：US09748414B2
公开(公告)日：2017-08-29
申请号：US13476955
申请日：2012-05-21
申请人： Arthur R. Zingher
发明人： Arthur R. Zingher
IPC分类号： H01L31/05 , H01L31/068 , H01L31/02 , H01L31/042
CPC分类号： H01L31/02021 , H01L31/02167 , H01L31/042 , H01L31/0443 , H01L31/05 , H01L31/0682 , Y02E10/547
摘要： A self-activated front surface bias for photovoltaic solar cell assembly is provided. The solar cell assembly comprises a front surface electrical bias activated by electrical energy generated by the solar cell assembly. The front surface bias improves generation efficiency for said solar cell assembly.

4. 发明授权

US07915699B2 Integrated circuit chip that supports through-chip electromagnetic communication 有权
标题翻译：集成电路芯片，支持片上电磁通讯
公开(公告)号：US07915699B2
公开(公告)日：2011-03-29
申请号：US11165809
申请日：2005-06-24
申请人： Ashok V. Krishnamoorthy , Arthur R. Zingher , Robert J. Drost
发明人： Ashok V. Krishnamoorthy , Arthur R. Zingher , Robert J. Drost
IPC分类号： H01L27/14
CPC分类号： G02B6/43 , H01L23/48 , H01L25/0652 , H01L25/0657 , H01L31/12 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic via that facilitates communication between signal pads on the integrated circuit chip and signal pads on a second integrated circuit chip. The electromagnetic via couples a signal pad on the active face of the integrated circuit chip to the back face of the integrated circuit chip so that the integrated circuit chip can communicate with the second integrated circuit chip while the back face of the integrated circuit chip is adjacent to the active face of the second integrated circuit chip. Moreover, the electromagnetic via operates by facilitating non-conductive signaling through the integrated circuit chip.
摘要翻译：本发明的一个实施例提供一种集成电路芯片，其包括有源电路和信号焊盘所在的有源面以及与有源面相对的背面。集成电路芯片还包括电磁通孔，其有助于集成电路芯片上的信号焊盘与第二集成电路芯片上的信号焊盘之间的通信。电磁通孔将集成电路芯片的有源面上的信号焊盘连接到集成电路芯片的背面，使得集成电路芯片可以与集成电路芯片的背面相邻的第二集成电路芯片连通到第二集成电路芯片的主动面。此外，电磁通孔通过促进通过集成电路芯片的非导电信号来操作。

5. 发明授权

US07397136B2 Multi-chip module and single-chip module for chips and proximity connectors 有权
标题翻译：用于芯片和接近连接器的多芯片模块和单芯片模块
公开(公告)号：US07397136B2
公开(公告)日：2008-07-08
申请号：US11183047
申请日：2005-07-15
申请人： Arthur R. Zingher , Bruce M. Guenin , Edward L. Follmer
发明人： Arthur R. Zingher , Bruce M. Guenin , Edward L. Follmer
IPC分类号： H01L23/48 , H01L23/52 , H01L29/14
CPC分类号： H04B5/0012 , H01L23/48 , H01L23/50 , H01L2224/32 , H01L2924/1461 , H01L2924/19041 , H01L2924/19104 , H01L2924/3011 , H01L2924/00
摘要： A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.
摘要翻译：描述了单芯片模块。该模块包括具有第一表面和第二表面的第一半导体管芯。第一半导体管芯被配置为通过电容耦合来使用耦合到第一半导体管芯的多个接近连接器中的一个或多个连接。耦合到第一半导体管芯的电缆被配置为将功率信号耦合到第一半导体管芯。电缆的至少一个部分的灵活性符合性大于阈值，从而允许模块定位在安装结构中。

6. 发明申请

US20080077780A1 System and Method for Software Debugging 审中-公开
标题翻译：软件调试的系统和方法
公开(公告)号：US20080077780A1
公开(公告)日：2008-03-27
申请号：US10565618
申请日：2004-07-23
申请人： Arthur R. Zingher
发明人： Arthur R. Zingher
IPC分类号： G06F9/00
CPC分类号： G06F11/3636 , G06F11/3648
摘要： The software debugging system provides a processor that is executing a software process, and the software process has a bug or other failure. A fast-response reporter circuit connects to a low level asset in the processor, such as a reorder buffer, commit buffer, or high speed data path. The fast response reporter circuit is configured to selectively extract data from the low-level asset, and the extracted data is transmitted to an evidence file for review and analysis. In one arrangement, a fast-response sentry circuit also connects to a low-level asset in the processor, and is configured to monitor for a predefined event. When the predefined event occurs, the fast-response sentry circuit causes an action to occur, such as activation of the reporter fast-response circuit.
摘要翻译：软件调试系统提供了一个正在执行软件过程的处理器，并且软件进程有一个错误或其他故障。快速响应记者电路连接到处理器中的低级别资产，例如重排序缓冲器，提交缓冲器或高速数据路径。快速响应报告器电路被配置为从低级别资产中选择性地提取数据，并将提取的数据传送到证据文件进行审查和分析。在一种安排中，快速响应报警电路还连接到处理器中的低级别资产，并且被配置为监视预定事件。当预定义的事件发生时，快速响应信号电路引起动作发生，例如报告器快速响应电路的激活。

7. 发明授权

US07332919B1 Method and apparatus for distributing signals over jig-plates 有权
标题翻译：用于在夹具板上分配信号的方法和装置
公开(公告)号：US07332919B1
公开(公告)日：2008-02-19
申请号：US11232843
申请日：2005-09-21
申请人： Ronald Ho , Robert J. Drost , Arthur R. Zingher
发明人： Ronald Ho , Robert J. Drost , Arthur R. Zingher
IPC分类号： G01R31/02
CPC分类号： H01L23/538 , H01L25/0655 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H05K1/0287 , H05K1/0289 , H05K1/183 , H05K2201/09254 , H05K2201/10674 , H01L2924/00
摘要： One embodiment of the present invention provides a system for distributing signals through a jig-plate in a computer system. The jig-plate contains alignment features that assist in positioning semiconductor chips in relation to the jig-plate. In addition, the jig-plate contains one or more embedded signal routing layers. These metal routing layers provide one or more signal routes for the distribution of signals through the jig-plate to semiconductor chips which have been aligned with the jig-plate. Note that routing the signals through the jig-plate facilitates the distribution of the signals without requiring that the signals be routed through the semiconductor chips in the jig-plate.
摘要翻译：本发明的一个实施例提供一种用于通过计算机系统中的夹具板来分配信号的系统。夹具板包含有助于相对于夹具板定位半导体芯片的对准特征。另外，夹具板包含一个或多个嵌入式信号路由层。这些金属布线层提供了一个或多个用于将通过夹具板的信号分配到已经与夹具板对准的半导体芯片的信号路线。注意，通过夹具板布置信号有助于信号的分配，而不需要信号通过夹具板中的半导体芯片布线。

8. 发明授权

US5388635A Compliant fluidic coolant hat 失效
标题翻译：符合流体冷却剂帽
公开(公告)号：US5388635A
公开(公告)日：1995-02-14
申请号：US883051
申请日：1992-05-08
申请人： Peter A. Gruber , Arthur R. Zingher
发明人： Peter A. Gruber , Arthur R. Zingher
IPC分类号： F28F3/12 , F28F27/02 , H01L23/433 , H01L23/473 , F28F7/00
CPC分类号： F28F9/0278 , F28F3/12 , H01L23/433 , H01L23/473 , F28D2021/0029 , F28F2210/02 , H01L2224/16 , H01L2224/73253 , H01L2924/01014 , H01L2924/13034 , H01L2924/1305 , H01L2924/3025 , H01L2924/3511
摘要： A cooling hat for transferring heat from a surface or plurality of heat generating components to a flowing fluid includes a coldsheet, a plurality of manifold layers and springs. The coldsheet is typically a medium-thin metal sheet usually with fine fins or grooves to readily transfer heat to a coolant. Each manifold layer is typically molded rubber with conduits for coolant supply and return. The conduits form a branched hierarchy. The fluid flow is highly parallel and streamlined which achieves ample flow with small hydraulic differential pressure. Springs gently urge the cooling hat against the thermal joints hence against the components. The hat can bend slightly to conform to a curved surface. Typically some compliance is provided by the hat, and other compliance is provided by a thermal joint between each component and the coldsheet. The system is highly self-aligned for counteracting variations.
摘要翻译：用于将热量从表面或多个发热部件传递到流动流体的冷却帽包括冷片，多个歧管层和弹簧。冷片通常是中等厚度的金属片，通常具有细的翅片或凹槽，以便将热量传递给冷却剂。每个歧管层通常是具有用于冷却剂供应和返回的导管的模制橡胶。导管形成分支层级。流体流动是高度平行和流线型的，其具有小的液压差压的充足的流量。弹簧轻轻地将冷却帽推向热接头，从而抵抗部件。帽子可以稍微弯曲以符合曲面。通常，帽子提供一些柔顺性，并且通过每个部件和冷片之间的热接头来提供其它柔顺性。该系统高度自我对齐以抵消变化。

9. 发明授权

US5310440A Convection transfer system 失效
标题翻译：对流传输系统
公开(公告)号：US5310440A
公开(公告)日：1994-05-10
申请号：US862160
申请日：1992-04-02
申请人： Arthur R. Zingher
发明人： Arthur R. Zingher
IPC分类号： C23F1/08 , C25D21/10 , F28D21/00 , F28F13/02 , F28F23/00 , H01L21/302 , H01L21/3065 , H01L23/44 , H01L23/473 , H01M8/02 , H05K3/00 , H05K3/06 , H05K3/18 , H01L21/00
CPC分类号： F28F13/02 , H01L23/445 , H01L23/4735 , H01M8/04074 , H01L2924/0002 , H05K3/0085
摘要： A system provides for convective transferring of material between a workpiece and a flowing fluid which chemically reacts with the workpiece. A gap is formed between the workpiece and a facesheet. The fluid is fed to supply nozzles, travels a short distance within the gap adjacent to the facesheet and exits via return nozzles. The flow cross section and flow density facilitate convective transfer at a moderate flow rate and low fluid pressure. The system is also applicable for chemical transfer such as plating or etching printed circuit boards.
摘要翻译：系统提供了在工件和与工件发生化学反应的流动流体之间的材料的对流传递。在工件和面板之间形成间隙。流体被供给到供应喷嘴，在与面板相邻的间隙内短距离行进，并通过返回喷嘴离开。流量横截面和流量密度便于中等流量和低流体压力下的对流传递。该系统也适用于电镀或蚀刻印刷电路板等化学转印。

10. 发明申请

US20130125950A1 SELF-ACTIVATED FRONT SURFACE BIAS FOR A SOLAR CELL 有权
标题翻译：用于太阳能电池的自激式前表面偏光
公开(公告)号：US20130125950A1
公开(公告)日：2013-05-23
申请号：US13476955
申请日：2012-05-21
申请人： Arthur R. Zingher
发明人： Arthur R. Zingher
IPC分类号： H01L31/02 , H01L31/05
CPC分类号： H01L31/02021 , H01L31/02167 , H01L31/042 , H01L31/0443 , H01L31/05 , H01L31/0682 , Y02E10/547
摘要： A self-activated front surface bias for photovoltaic solar cell assembly is provided. The solar cell assembly comprises a front surface electrical bias activated by electrical energy generated by the solar cell assembly. The front surface bias improves generation efficiency for said solar cell assembly.
摘要翻译：提供了一种用于光伏太阳能电池组件的自激活前表面偏压。太阳能电池组件包括由太阳能电池组件产生的电能激活的前表面电偏压。前表面偏压提高了所述太阳能电池组件的发电效率。

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