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1. 发明授权

US07635867B2 Nanotube array and method for producing a nanotube array 失效
标题翻译：纳米管阵列及其制造方法
公开(公告)号：US07635867B2
公开(公告)日：2009-12-22
申请号：US10476663
申请日：2002-05-16
申请人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
发明人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
IPC分类号： H01L31/0312
CPC分类号： H01L51/0048 , B82Y10/00 , C01B32/05 , G01N27/127 , G11C13/025 , H01L51/0595
摘要： A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.
摘要翻译：纳米管阵列及其制造方法。纳米管阵列具有衬底，催化剂层，其包括在衬底的表面上的一个或多个子区域，和布置在催化剂层表面上的平行于衬底表面的至少一个纳米管。所述至少一个纳米管平行于衬底的表面布置，导致至少一个纳米管的平面布置。因此，本发明的纳米管阵列适用于与传统的硅微电子耦合。因此，根据本发明，可以将纳米管阵列电连接到宏观半导体电子器件。此外，根据本发明的纳米管阵列可以在衬底和催化剂层之间具有电绝缘层。该电绝缘层优选地具有使得至少一个纳米管在其端部部分处于电绝缘层上并且在其中心部分未被覆盖的形貌。由于至少一个纳米管的表面部分未被覆盖，纳米管的未被覆盖的表面可以用作主动传感器表面。例如，纳米管的未覆盖表面可以与围绕纳米管阵列的气氛进行操作接触。在某些气体的存在下，纳米管的电阻显着变化。因此，由于纳米管是透明和未覆盖的，所以纳米管阵列可用于许多传感器应用中。

2. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

3. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

4. 发明申请

US20050276093A1 Memory cell, memory cell arrangement, patterning arrangement, and method for fabricating a memory cell 审中-公开
标题翻译：存储单元，存储单元布置，图案化布置以及用于制造存储单元的方法
公开(公告)号：US20050276093A1
公开(公告)日：2005-12-15
申请号：US11119531
申请日：2005-04-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , G11C11/24
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： A memory cell having a storage capacitor and a vertical switching transistorm, which has a semiconducting nanostructure which has grown on at least part of the storage capacitor and includes a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.
摘要翻译：具有存储电容器和垂直开关转置管的存储单元，其具有在至少部分存储电容器上生长的半导体纳米结构，并且包括半导体纳米管，半导体纳米管束或半导体纳米棒。

5. 发明申请

US20060175666A1 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
公开(公告)号：US20060175666A1
公开(公告)日：2006-08-10
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

6. 发明申请

US20070096196A1 Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement 有权
标题翻译：翅片场效应晶体管布置及其制造方法
公开(公告)号：US20070096196A1
公开(公告)日：2007-05-03
申请号：US11588868
申请日：2006-10-27
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken
IPC分类号： H01L29/788 , H01L21/84 , H01L21/8238 , H01L27/12 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785 , H01L29/78636
摘要： A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.
摘要翻译：鳍状场效应晶体管布置包括衬底和衬底上和/或衬底中的第一鳍状场效应晶体管。第一鳍状场效应晶体管包括鳍状物，其中在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域，并且在其上形成栅极区域。第二鳍状场效应晶体管设置在衬底上和/或衬底中，包括在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域的鳍片，并且在其上形成栅极区域。第二鳍状场效应晶体管沿第一鳍状场效应晶体管横向布置，其中第一鳍状场效应晶体管的鳍的高度大于第二鳍状场效应晶体管的鳍的高度。

7. 发明申请

US20050199912A1 Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells 失效
标题翻译：具有垂直存储晶体管的半导体存储器，其具有1-2F2个单元阵列
公开(公告)号：US20050199912A1
公开(公告)日：2005-09-15
申请号：US11073214
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/73 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.
摘要翻译：本发明涉及一种具有多个存储单元的半导体存储器，每个存储器单元具有N（例如四个）垂直存储晶体管，具有捕获层。在相对于单元阵列的行和列倾斜地延伸的较高半导体区域中形成更高的接触区域，栅电极通常被引导到较高半导体区域的台阶侧区域。因此可以实现每位1-2F 2的存储密度。

8. 发明申请

US20080054324A1 INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE 有权
标题翻译：集成电路，包括门电极
公开(公告)号：US20080054324A1
公开(公告)日：2008-03-06
申请号：US11926653
申请日：2007-10-29
申请人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
发明人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅电极在至少两个相对的两侧包围沟道层。

9. 发明申请

US20050110088A1 Substrate and method for producing a substrate 有权
标题翻译：基板及其制造方法
公开(公告)号：US20050110088A1
公开(公告)日：2005-05-26
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

10. 发明申请

US20060022248A1 Electronic data memory device for a high read current 审中-公开
标题翻译：用于高读取电流的电子数据存储器件
公开(公告)号：US20060022248A1
公开(公告)日：2006-02-02
申请号：US11167386
申请日：2005-06-27
申请人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
发明人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , H01L29/7851
摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).
摘要翻译：用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200）晶体管（300），用于选择存储单元（100）。选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。

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