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1. 发明申请

US20060175666A1 Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权
公开(公告)号：US20060175666A1
公开(公告)日：2006-08-10
申请号：US11324803
申请日：2006-01-03
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

2. 发明申请

US20050110088A1 Substrate and method for producing a substrate 有权
标题翻译：基板及其制造方法
公开(公告)号：US20050110088A1
公开(公告)日：2005-05-26
申请号：US10968846
申请日：2004-10-18
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Stadele
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/76254
摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
摘要翻译：衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。在半导体层上形成晶体管。

3. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

4. 发明申请

US20060267082A1 Semiconductor memory component 失效
标题翻译：半导体存储器组件
公开(公告)号：US20060267082A1
公开(公告)日：2006-11-30
申请号：US11438883
申请日：2006-05-23
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner , Michael Specht , Martin Staedele
IPC分类号： H01L29/76
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译：半导体存储器组件包括至少一个存储单元。存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

5. 发明申请

US20050276093A1 Memory cell, memory cell arrangement, patterning arrangement, and method for fabricating a memory cell 审中-公开
标题翻译：存储单元，存储单元布置，图案化布置以及用于制造存储单元的方法
公开(公告)号：US20050276093A1
公开(公告)日：2005-12-15
申请号：US11119531
申请日：2005-04-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , G11C11/24
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： A memory cell having a storage capacitor and a vertical switching transistorm, which has a semiconducting nanostructure which has grown on at least part of the storage capacitor and includes a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.
摘要翻译：具有存储电容器和垂直开关转置管的存储单元，其具有在至少部分存储电容器上生长的半导体纳米结构，并且包括半导体纳米管，半导体纳米管束或半导体纳米棒。

6. 发明申请

US20050186738A1 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US20050186738A1
公开(公告)日：2005-08-25
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H01R11/22 , H01R13/62
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

7. 发明申请

US20050100938A1 Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement 审中-公开
标题翻译：垂直阻抗传感器布置和垂直阻抗传感器布置方法
公开(公告)号：US20050100938A1
公开(公告)日：2005-05-12
申请号：US10939319
申请日：2004-09-09
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
IPC分类号： C12Q1/68 , G01N33/543
CPC分类号： G01N33/54386 , G01N27/3276
摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.
摘要翻译：垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

8. 发明申请

US20050199912A1 Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells 失效
标题翻译：具有垂直存储晶体管的半导体存储器，其具有1-2F2个单元阵列
公开(公告)号：US20050199912A1
公开(公告)日：2005-09-15
申请号：US11073214
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/73 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.
摘要翻译：本发明涉及一种具有多个存储单元的半导体存储器，每个存储器单元具有N（例如四个）垂直存储晶体管，具有捕获层。在相对于单元阵列的行和列倾斜地延伸的较高半导体区域中形成更高的接触区域，栅电极通常被引导到较高半导体区域的台阶侧区域。因此可以实现每位1-2F 2的存储密度。

9. 发明申请

US20080054324A1 INTEGRATED CIRCUIT INCLUDING A GATE ELECTRODE 有权
标题翻译：集成电路，包括门电极
公开(公告)号：US20080054324A1
公开(公告)日：2008-03-06
申请号：US11926653
申请日：2007-10-29
申请人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
发明人： Richard Luyken , Franz Hofmann , Lothar Risch , Dirk Manger , Wolfgang Rosner , Till Schloesser , Michael Specht
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/10808 , H01L27/10826 , H01L27/10829 , H01L27/10891 , H01L29/7851
摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
摘要翻译：公开了一种包括栅电极的集成电路。一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。在半导体衬底中的第一和第二源极/漏极之间布置有沟道。栅电极被布置在沟道层附近并且与沟道层电绝缘。半导体基板电极设置在后侧。栅电极在至少两个相对的两侧包围沟道层。

10. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

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