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1. 发明授权

US06239591B1 Method and apparatus for monitoring SOI hysterises effects 失效
标题翻译：监测SOI隔音效应的方法和装置
公开(公告)号：US06239591B1
公开(公告)日：2001-05-29
申请号：US09303358
申请日：1999-04-29
申请人： Andres Bryant , Edward J. Nowak , Minh Ho Tong
发明人： Andres Bryant , Edward J. Nowak , Minh Ho Tong
IPC分类号： G01R1955
CPC分类号： H01L22/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for measuring hysteresis effects of a wafer process. The method comprises steps of generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.
摘要翻译：一种用于测量晶圆工艺的滞后效应的系统和方法。该方法包括以下步骤：产生具有等于延迟链的转变的延迟的脉冲宽度的脉冲，其中延迟链处于静态条件下相当长的时间; 对在环状振荡器已经在稳态条件下操作的脉冲宽度期间产生的环形振荡器进行计数; 将振荡次数与期望值进行比较; 并且将由比较步骤产生的差与由晶片工艺影响的滞后水平相关联。

2. 发明授权

US06054354A High voltage field effect transistors with selective gate depletion 失效
标题翻译：具有选择性栅极耗尽的高电压场效应晶体管
公开(公告)号：US06054354A
公开(公告)日：2000-04-25
申请号：US014889
申请日：1998-01-28
申请人： Edward J. Nowak , Minh Ho Tong
发明人： Edward J. Nowak , Minh Ho Tong
IPC分类号： H01L21/8234 , H01L21/8236 , H01L21/8238 , H01L27/088 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/8236
摘要： A method of forming field effect transistors (FETS) on a silicon wafer. A gate layer, polysilicon, is formed on a gate dielectric layer (oxide) on the silicon wafer. High voltage device locations are defined and blocked while normal NFETs and PFETs are formed. If the FET process is a gate predope process, the gate layer is blocked during predoping and patterned after the predoping is complete. Otherwise, the gate layer is patterned prior to doping. After gate definition, high voltage FETs are unblocked and implanted with a dopant, preferably boron (B) or (P), which dopes gates and source/drain regions such that they are depleted, resulting in a thicker effective gate dielectric than normal NFETs and PFETs.
摘要翻译：一种在硅晶片上形成场效应晶体管（FETS）的方法。在硅晶片上的栅介质层（氧化物）上形成栅极层，多晶硅。当形成正常的NFET和PFET时，高压器件位置被定义和阻挡。如果FET工艺是栅极预处理工艺，则栅极层在预处理期间被封闭，并且在预取完成之后进行图案化。否则，在掺杂之前栅极层被图案化。在栅极定义之后，高压FET被解锁并且注入掺杂剂，优选硼（B）或（P），其掺杂栅极和源极/漏极区域，使得它们被耗尽，导致比正常NFET更厚的有效栅极电介质， PFET。

3. 发明授权

US06404236B1 Domino logic circuit having multiplicity of gate dielectric thicknesses 有权
标题翻译：具有多个栅介质厚度的多米诺逻辑电路
公开(公告)号：US06404236B1
公开(公告)日：2002-06-11
申请号：US09811967
申请日：2001-03-19
申请人： Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
发明人： Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.
摘要翻译：公开了具有时钟预充电的多米诺骨牌逻辑电路。多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。连接到电源，预充电晶体管接收时钟输入。隔离晶体管连接到地，并接收时钟输入。耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。

4. 发明授权

US06512269B1 High-voltage high-speed SOI MOSFET 有权
标题翻译：高压高速SOI MOSFET
公开(公告)号：US06512269B1
公开(公告)日：2003-01-28
申请号：US09657315
申请日：2000-09-07
申请人： Andres Bryant , Edward Joseph Nowak , Minh Ho Tong
发明人： Andres Bryant , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L29/42384
摘要： A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.
摘要翻译：一种包括SOI衬底的半导体器件; 衬底中的多个扩散区域，分隔并邻接所述衬底中的多个主体区域，身体区域中的第一个和其邻接扩散区域具有第一宽度和连续的身体区域及其邻接扩散区域具有相继较小的宽度; 以及多个栅极，每个栅极分别位于多个主体区域中的一个上，并且通过电介质材料与主体区域分离，所述多个栅极连接到公共电压端子。

5. 发明授权

US06365484B1 Method of forming semiconductor device with decoupling capacitance 失效
标题翻译：用去耦电容形成半导体器件的方法
公开(公告)号：US06365484B1
公开(公告)日：2002-04-02
申请号：US09634970
申请日：2000-08-09
申请人： Edward Joseph Nowak , Minh Ho Tong
发明人： Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2120
CPC分类号： H01L27/1203 , H01L27/0248 , H01L27/088
摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.
摘要翻译：公开了提供一种去耦电容的半导体器件及其方法。半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

6. 发明授权

US6057184A Semiconductor device fabrication method using connecting implants 失效
标题翻译：使用连接植入物的半导体器件制造方法
公开(公告)号：US6057184A
公开(公告)日：2000-05-02
申请号：US821553
申请日：1997-03-21
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
IPC分类号： H01L21/74 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/743 , H01L27/0928
摘要： A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.
摘要翻译：一种用于这种器件的半导体器件和制造方法，其中P-外延层位于P ++衬底之上。 P ++掩埋层植入物位于P ++衬底和P-外延层之间的器件内。将连接的p +植入物放置在掩埋的p +覆盖层植入物上方的外延层内。在一个示例性实施例中，该器件包括浅P阱，其中P +连接植入物位于连接浅P阱和掩埋P +覆盖植入层的外延层内的位置。

7. 发明授权

US5831452A Leak tolerant low power dynamic circuits 失效
标题翻译：耐漏电低功率动态电路
公开(公告)号：US5831452A
公开(公告)日：1998-11-03
申请号：US803582
申请日：1997-02-20
申请人： Edward Joseph Nowak , Minh Ho Tong , Lawrence G. Heller
发明人： Edward Joseph Nowak , Minh Ho Tong , Lawrence G. Heller
IPC分类号： H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.
摘要翻译：为动态CMOS逻辑电路提供了一种新颖的预充电电路，其免于漏电流并降低总体功耗。电路包括用于在待机模式期间将节点预充电到指示第一逻辑状态的高电压电平的预充电晶体管。此后，在活动模式期间，节点可以被连接的逻辑电路放电，也可以不被放电。如果节点放电，则提供附加晶体管以在随后的待机模式期间禁止已经充电的节点的预充电。类似地，如果节点不被放电，则提供小的保持晶体管以保持节点处于完全预充电电平。

8. 发明授权

US06239649B1 Switched body SOI (silicon on insulator) circuits and fabrication method therefor 失效
标题翻译：开关体SOI（绝缘体上硅）电路及其制造方法
公开(公告)号：US06239649B1
公开(公告)日：2001-05-29
申请号：US09295124
申请日：1999-04-20
申请人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
发明人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
IPC分类号： G05F302
CPC分类号： H03K19/0027 , H01L29/78606 , H03K2217/0018
摘要： Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.
摘要翻译：具有SOI器件的电路通过用于选择性地将体偏置电压信号连接到SOI器件主体的开关耦合到体偏置电压。 NMOS或PMOS SOI器件用于开关体SOI器件，FET用于开关，SOI器件的栅极端子连接到FET器件。 SOI器件的栅极将FET偏置电压信号的FET开关连接控制到SOI器件以调整SOI器件的阈值。还公开了并入SOI器件的逻辑电路，以及SOI器件的制造工艺。

9. 发明授权

US06459106B2 Dynamic threshold voltage devices with low gate to substrate resistance 有权
标题翻译：动态门限电压器件具有低栅极到衬底电阻
公开(公告)号：US06459106B2
公开(公告)日：2002-10-01
申请号：US09753521
申请日：2001-01-03
申请人： Andres A. Bryant , Edward Joseph Nowak , Minh Ho Tong
发明人： Andres A. Bryant , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L29768
CPC分类号： H01L21/84 , H01L29/78609 , H01L29/78612
摘要： Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.
摘要翻译：描述了一种动态阈值场效应晶体管（DTFET），其包括栅极内的栅对体接触结构。通过形成能够降低栅对体接触电阻并增加器件封装密度的栅对体接触结构，DTFET可用于绝缘体上硅（SOI）技术，并充分利用了DT-CMOS 性能优势。

10. 发明授权

US06191451B1 Semiconductor device with decoupling capacitance 失效
标题翻译：具有去耦电容的半导体器件
公开(公告)号：US06191451B1
公开(公告)日：2001-02-20
申请号：US09016026
申请日：1998-01-30
申请人： Edward Joseph Nowak , Minh Ho Tong
发明人： Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/0248 , H01L27/088
摘要： A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.
摘要翻译：公开了提供一种去耦电容的半导体器件及其方法。半导体器件包括具有在隔离层上的第一器件层的第一电路区域和与第一电路区域相邻的第二电路区域，该第二电路区域在阱上具有第二器件层。在第一电路区域中的隔离层下方植入注入层，其将连接到第二电路区域的阱。

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