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1. 发明授权

US6057184A Semiconductor device fabrication method using connecting implants 失效
标题翻译：使用连接植入物的半导体器件制造方法
公开(公告)号：US6057184A
公开(公告)日：2000-05-02
申请号：US821553
申请日：1997-03-21
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
IPC分类号： H01L21/74 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823892 , H01L21/743 , H01L27/0928
摘要： A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.
摘要翻译：一种用于这种器件的半导体器件和制造方法，其中P-外延层位于P ++衬底之上。 P ++掩埋层植入物位于P ++衬底和P-外延层之间的器件内。将连接的p +植入物放置在掩埋的p +覆盖层植入物上方的外延层内。在一个示例性实施例中，该器件包括浅P阱，其中P +连接植入物位于连接浅P阱和掩埋P +覆盖植入层的外延层内的位置。

2. 发明授权

US6097068A Semiconductor device fabrication method and apparatus using connecting implants 失效
标题翻译：使用连接植入物的半导体器件制造方法和装置
公开(公告)号：US6097068A
公开(公告)日：2000-08-01
申请号：US10870
申请日：1998-01-22
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert John Gauthier, Jr. , Xiaowei Tian , Minh Ho Tong , Steven Howard Voldman
IPC分类号： H01L21/74 , H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823892 , H01L21/743 , H01L27/0928
摘要： A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.
摘要翻译：一种用于这种器件的半导体器件和制造方法，其中P-外延层位于P ++衬底之上。 P ++掩埋层植入物位于P ++衬底和P-外延层之间的器件内。将连接的p +植入物放置在掩埋的p +覆盖层植入物上方的外延层内。在一个示例性实施例中，该器件包括浅P阱，其中P +连接植入物位于连接浅P阱和掩埋P +覆盖植入层的外延层内的位置。

3. 发明授权

US5896303A Discretization technique for multi-dimensional semiconductor device simulation 失效
标题翻译：多维半导体器件仿真的离散化技术
公开(公告)号：US5896303A
公开(公告)日：1999-04-20
申请号：US729464
申请日：1996-10-11
申请人： Stephen Scott Furkay , Jeffrey Bowman Johnson
发明人： Stephen Scott Furkay , Jeffrey Bowman Johnson
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5018
摘要： Disclosed is a method of improved grid generation for semiconductor device simulation. In particular, the invention includes a simple method for locating critical interfaces (e.g., oxide-silicon interfaces) and then utilizing the information to generate finer mesh elements near those boundaries where device behavior is most critical. The method of identifying critical interfaces includes the steps of examining the boundary data for each material region in the device, and then generating normal lines between adjacent boundaries to identify "thin" regions, which are generally associated with the critical interfaces. Once this occurs, a recursive subdivision algorithm may be utilized to generate a grid whose element dimensions are dependent upon their proximity to identified critical regions.
摘要翻译：公开了一种改进半导体器件仿真网格生成的方法。特别地，本发明包括用于定位关键界面（例如，氧化硅接口）的简单方法，然后利用该信息在设备行为最关键的边界附近生成更细的网格元素。识别关键接口的方法包括检查设备中每个材料区域的边界数据的步骤，然后在相邻边界之间生成法线，以识别通常与关键接口相关联的“薄”区域。一旦发生这种情况，可以使用递归细分算法来生成其元素尺寸取决于其与所识别的关键区域的接近度的网格。

4. 发明授权

US06486510B2 Reduction of reverse short channel effects by implantation of neutral dopants 失效
标题翻译：通过植入中性掺杂剂减少反向短通道效应
公开(公告)号：US06486510B2
公开(公告)日：2002-11-26
申请号：US10054297
申请日：2001-11-12
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
IPC分类号： H01L310288
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/105 , H01L29/1079 , H01L29/66575
摘要： A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.
摘要翻译：描述了具有减小的反向短通道效应的FET，以及制造所述FET的方法。以强度和剂量将锗植入整个半导体衬底，使得在FET的源极和漏极之下产生峰值离子浓度。锗可以在栅极和源极和漏极形成之前被植入，并且减少FET中通常看到的反向短沟道效应。通常在FET中发生的短沟道效应不会受到锗植入物的负面影响。

5. 发明授权

US06352912B1 Reduction of reverse short channel effects by deep implantation of neutral dopants 有权
标题翻译：通过深度植入中性掺杂剂减少反向短通道效应
公开(公告)号：US06352912B1
公开(公告)日：2002-03-05
申请号：US09539527
申请日：2000-03-30
申请人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
发明人： Jeffrey Scott Brown , Stephen Scott Furkay , Robert J. Gauthier, Jr. , Dale Warner Martin , James Albert Slinkman
IPC分类号： H01L21265
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/105 , H01L29/1079 , H01L29/66575
摘要： A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.
摘要翻译：描述了具有减小的反向短通道效应的FET，以及制造所述FET的方法。以强度和剂量将锗植入整个半导体衬底，使得在FET的源极和漏极之下产生峰值离子浓度。锗可以在栅极和源极和漏极形成之前被植入，并且减少FET中通常看到的反向短沟道效应。通常在FET中发生的短沟道效应不会受到锗植入物的负面影响。

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