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1. 发明授权

US07470959B2 Integrated circuit structures for preventing charging damage 有权
标题翻译：用于防止充电损坏的集成电路结构
公开(公告)号：US07470959B2
公开(公告)日：2008-12-30
申请号：US11275482
申请日：2006-01-09
申请人： Terence Blackwell Hook , Jeffery Scott Zimmerman
发明人： Terence Blackwell Hook , Jeffery Scott Zimmerman
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , G06F17/5045 , H01L21/84
摘要： Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.
摘要翻译：公开了一种用于防止集成电路设计中的充电损坏的电路，例如具有硅绝缘体（SOI）晶体管的设计。该电路通过向IC设计分配区域来防止在处理到IC器件的栅极期间的充电损坏，使得位于区域内的器件具有电独立的网络，识别可能在源极或漏极之间具有电压差的器件，以及栅极作为给定区域内的敏感装置，并且跨过源极或漏极以及每个敏感装置的栅极连接元件，使得元件位于该区域内。或者，方法/电路提供将补偿导体连接到元件以消除潜在的充电损坏。

2. 发明授权

US06239649B1 Switched body SOI (silicon on insulator) circuits and fabrication method therefor 失效
标题翻译：开关体SOI（绝缘体上硅）电路及其制造方法
公开(公告)号：US06239649B1
公开(公告)日：2001-05-29
申请号：US09295124
申请日：1999-04-20
申请人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
发明人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
IPC分类号： G05F302
CPC分类号： H03K19/0027 , H01L29/78606 , H03K2217/0018
摘要： Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.
摘要翻译：具有SOI器件的电路通过用于选择性地将体偏置电压信号连接到SOI器件主体的开关耦合到体偏置电压。 NMOS或PMOS SOI器件用于开关体SOI器件，FET用于开关，SOI器件的栅极端子连接到FET器件。 SOI器件的栅极将FET偏置电压信号的FET开关连接控制到SOI器件以调整SOI器件的阈值。还公开了并入SOI器件的逻辑电路，以及SOI器件的制造工艺。

3. 发明申请

US20110278674A1 TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION 审中-公开
标题翻译： TRENCH分离和制备TRENCH隔离的方法
公开(公告)号：US20110278674A1
公开(公告)日：2011-11-17
申请号：US13192561
申请日：2011-07-28
申请人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
发明人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76224 , H01L21/76237 , H01L21/76283 , H01L21/82 , H01L21/823878 , H01L21/823892
摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.
摘要翻译：沟槽隔离结构和形成沟槽隔离结构的方法。所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

4. 发明申请

US20090045468A1 TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION 有权
标题翻译： TRENCH分离和制备TRENCH隔离的方法
公开(公告)号：US20090045468A1
公开(公告)日：2009-02-19
申请号：US11839585
申请日：2007-08-16
申请人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
发明人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76224 , H01L21/76237 , H01L21/76283 , H01L21/82 , H01L21/823878 , H01L21/823892
摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.
摘要翻译：沟槽隔离结构和形成沟槽隔离结构的方法。所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

5. 发明授权

US08012848B2 Trench isolation and method of fabricating trench isolation 有权
标题翻译：沟槽隔离和制造沟槽隔离的方法
公开(公告)号：US08012848B2
公开(公告)日：2011-09-06
申请号：US11839585
申请日：2007-08-16
申请人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
发明人： Terence Blackwell Hook , Jeffrey Bowman Johnson , James Spiros Nakos
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76237 , H01L21/76283 , H01L21/82 , H01L21/823878 , H01L21/823892
摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.
摘要翻译：沟槽隔离结构和形成沟槽隔离结构的方法。所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

6. 发明授权

US06670683B2 Composite transistor having a slew-rate control 失效
公开(公告)号：US06670683B2
公开(公告)日：2003-12-30
申请号：US09754156
申请日：2001-01-04
申请人： Kerry Bernstein , Anthony Correale, Jr. , Terence Blackwell Hook , Douglas Willard Stout
发明人： Kerry Bernstein , Anthony Correale, Jr. , Terence Blackwell Hook , Douglas Willard Stout
IPC分类号： H01L2976
CPC分类号： H01L29/1041
摘要： A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

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