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1. 发明申请

US20070205430A1 METHOD AND STRUCTURE OF REFRACTORY METAL REACH THROUGH IN BIPOLAR TRANSISTOR 审中-公开
标题翻译：在双极晶体管中通过金属REACH的方法和结构
公开(公告)号：US20070205430A1
公开(公告)日：2007-09-06
申请号：US11276510
申请日：2006-03-03
申请人： David Collins , Louis Lanzerotti , Edward Nowark , Steven Voldman
发明人： David Collins , Louis Lanzerotti , Edward Nowark , Steven Voldman
IPC分类号： H01L31/111
CPC分类号： H01L29/7371 , H01L29/41708
摘要： Structure and method of structure in which a contact, e.g., low resistance; ohmic; resulting in Schottky isolation, is coupled to a doped region that is buried in a substrate. In a bipolar transistor having a collector region formed below an upper surface of a substrate, a trench is formed through a portion of the collector region, and the sidewall(s) and/or bottom of the trench are doped, e.g., by ion implantation or dopant. The trench is filled with a conductor, e.g., a refractory metal such as tungsten.
摘要翻译：结构的结构和方法，其中接触，例如低电阻; 欧姆导致肖特基隔离，被耦合到掩埋在衬底中的掺杂区域。在具有形成在衬底的上表面下方的集电极区域的双极晶体管中，通过集电极区域的一部分形成沟槽，并且例如通过离子注入掺杂沟槽的侧壁和/或底部或掺杂剂。沟槽填充有诸如钨等难熔金属的导体。

2. 发明申请

US20060270203A1 VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES 失效
标题翻译：变化的设备的破坏电压的变化区域形成
公开(公告)号：US20060270203A1
公开(公告)日：2006-11-30
申请号：US10908884
申请日：2005-05-31
申请人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
发明人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
IPC分类号： H01L21/425
CPC分类号： H01L21/8222 , H01L21/266 , H01L27/0825 , H01L29/0821 , H01L29/36
摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
摘要翻译：公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。还公开了一种半导体器件。

3. 发明申请

US20060157824A1 Semiconductor device and method having multiple subcollectors formed on a common wafer 有权
公开(公告)号：US20060157824A1
公开(公告)日：2006-07-20
申请号：US11299682
申请日：2005-12-13
申请人： James Dunn , Louis Lanzerotti , Steven Voldman
发明人： James Dunn , Louis Lanzerotti , Steven Voldman
IPC分类号： H01L27/082
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/0821
摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

4. 发明申请

US20060060856A1 HIGH-MOBILITY BULK SILICON PFET 失效
标题翻译：高移动硅片PFET
公开(公告)号：US20060060856A1
公开(公告)日：2006-03-23
申请号：US10711453
申请日：2004-09-20
申请人： Brent Anderson , Louis Lanzerotti , Edward Nowak
发明人： Brent Anderson , Louis Lanzerotti , Edward Nowak
IPC分类号： H01L29/76 , H01L21/84
CPC分类号： H01L29/0847 , H01L21/8213 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/0653 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。该场效应晶体管包括：形成在栅极电介质层的顶表面上的栅电极，单晶硅沟道区的顶表面上的栅介质层，顶表面上的单晶硅沟道区包含Ge的层，在单晶硅衬底的顶表面上的Ge包括层，在单晶硅衬底的顶表面上的第一介电层和第二电介质层之间的Ge包括层。

5. 发明申请

US20050051798A1 Silicon germanium heterojunction bipolar transistor with carbon incorporation 有权
标题翻译：具有碳掺入的硅锗异质结双极晶体管
公开(公告)号：US20050051798A1
公开(公告)日：2005-03-10
申请号：US10660048
申请日：2003-09-11
申请人： Louis Lanzerotti , Brian Ronan , Steven Voldman
发明人： Louis Lanzerotti , Brian Ronan , Steven Voldman
IPC分类号： H01H85/47 , H01L21/328 , H01L21/331 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/66242 , H01H85/47 , H01L29/7378
摘要： A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.
摘要翻译：硅锗异质结双极晶体管器件和方法包括半导体区域和半导体区域中的扩散区域，其中扩散区域是硼掺杂的，其中半导体区域包括其中的碳掺杂剂以最小化硼扩散，并且其中组合的掺杂剂的量，硼的量和半导体区域的尺寸使得扩散区域具有小于约4Kohms / cm 2的薄层电阻。此外，扩散区域以1×10 20 / cm 3至1×10 21 / cm 3的浓度进行硼掺杂。另外，半导体区域包括5-25％的锗和0-3％的碳。通过向半导体区域添加碳，该器件实现了静电放电鲁棒性，这进一步导致器件的功率故障分布更严格，并且增加了临界厚度并降低了半导体区域的热应变。

6. 发明申请

US20080099787A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080099787A1
公开(公告)日：2008-05-01
申请号：US11873696
申请日：2007-10-17
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/06
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

7. 发明申请

US20070096257A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070096257A1
公开(公告)日：2007-05-03
申请号：US11163882
申请日：2005-11-02
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/102
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

8. 发明申请

US20070093210A1 Methods and Apparatus for Mitigating the Effects of Solar Noise and the Like on a Wireless Communication System 有权
标题翻译：减轻太阳能噪声等对无线通信系统影响的方法与装置
公开(公告)号：US20070093210A1
公开(公告)日：2007-04-26
申请号：US11612920
申请日：2006-12-19
申请人： Gregory Kochanski , Louis Lanzerotti , George Rittenhouse , David Thomson
发明人： Gregory Kochanski , Louis Lanzerotti , George Rittenhouse , David Thomson
IPC分类号： H04B1/00 , H04B17/00
CPC分类号： H04W24/00 , H04W52/20 , H04W52/24 , H04W52/34
摘要： Techniques for reducing or eliminating effects of noise on a wireless communication system are provided. In one aspect of the invention, the technique comprises monitoring noise attributable to an interference source that may affect one or more components of the wireless communication system. The interference source being monitored is distant from the wireless communication system to the degree that noise arrives at the wireless communication system within a substantially point source-like angular range. For example, the noise may be attributable to the sun or tropospheric ducting. The technique then comprises initiating one or more operations, as a function of the monitored noise, to reduce or eliminate the effects of the noise attributable to the distant interference source at one or more of the components of the wireless communication system that are determined to be affected by such noise.
摘要翻译：提供了用于减少或消除噪声对无线通信系统的影响的技术。在本发明的一个方面中，该技术包括监测可能影响无线通信系统的一个或多个组件的可能受到干扰源的噪声。所监视的干扰源远离无线通信系统，到达噪声到达无线通信系统的程度，在基本上类似点的角度范围内。例如，噪音可能归因于太阳或对流层管道。该技术包括作为所监视的噪声的函数启动一个或多个操作，以减少或消除归因于远程干扰源的噪声对被确定为无线通信系统的一个或多个组件的影响受这种噪音影响。

9. 发明申请

US20060160292A1 NFET and PFET devices and methods of fabricating same 有权
标题翻译： NFET和PFET器件及其制造方法
公开(公告)号：US20060160292A1
公开(公告)日：2006-07-20
申请号：US11378786
申请日：2006-03-17
申请人： Brent Anderson , Louis Lanzerotti , Edward Nowak
发明人： Brent Anderson , Louis Lanzerotti , Edward Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/8213 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/0653 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。该场效应晶体管包括：形成在栅极电介质层的顶表面上的栅电极，单晶硅沟道区的顶表面上的栅介质层，顶表面上的单晶硅沟道区包含Ge的层，在单晶硅衬底的顶表面上的Ge包括层，在单晶硅衬底的顶表面上的第一介电层和第二电介质层之间的Ge包括层。

10. 发明申请

US20060154440A1 FORMING CHANNEL STOP FOR DEEP TRENCH ISOLATION PRIOR TO DEEP TRENCH ETCH 失效
公开(公告)号：US20060154440A1
公开(公告)日：2006-07-13
申请号：US10905627
申请日：2005-01-13
申请人： Louis Lanzerotti , Stephen St. Onge
发明人： Louis Lanzerotti , Stephen St. Onge
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/76237 , H01L29/78
摘要： Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.

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