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    • 2. 发明授权
    • Planar circuit optimization
    • 平面电路优化
    • US07261982B2
    • 2007-08-28
    • US10736295
    • 2003-12-15
    • Barthelemy FondeurAnca L. SalaRobert J. BrainardDavid K. NakamotoTom TruongSanjay M. ThekdiAnantharaman Vaidyanathan
    • Barthelemy FondeurAnca L. SalaRobert J. BrainardDavid K. NakamotoTom TruongSanjay M. ThekdiAnantharaman Vaidyanathan
    • G03F1/00G03C5/00
    • G03F7/70466G03F1/50G03F1/70
    • The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.
    • 本申请涉及使用光刻掩模组,光刻掩模组以及用光刻掩模组制造的平面电路制造平面电路的方法。 本发明涉及将光刻掩模分为两部分,即主掩模和一个或多个从属掩模。 主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。 特别地,主掩模用作模板以提供用于平面电路的总体布局,而每个从屏蔽被改变以调谐和/或定制平面电路。 由于只有一小部分平面电路被重新设计和/或重写为新的掩模(即,从属掩模),本发明提供了一种用于优化平面电路的简单且成本有效的方法。 此外,由于大多数掩模错误将源自主掩模,本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。
    • 6. 发明申请
    • Planar circuit optimization
    • 平面电路优化
    • US20050031968A1
    • 2005-02-10
    • US10736295
    • 2003-12-15
    • Barthelemy FondeurAnca SalaRobert BrainardDavid NakamotoTom TruongSanjay ThekdiAnantharaman Vaidyanathan
    • Barthelemy FondeurAnca SalaRobert BrainardDavid NakamotoTom TruongSanjay ThekdiAnantharaman Vaidyanathan
    • G03C5/00G03F1/14G03F7/20G03F9/00
    • G03F7/70466G03F1/50G03F1/70
    • The present application relates to a method of fabricating planar circuits using a photolithographic mask set, to the photolithographic mask set, and to a planar circuit fabricated with the photolithographic mask set. The instant invention involves separating a photolithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photolithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.
    • 本申请涉及使用光刻掩模组,光刻掩模组以及用光刻掩模组制造的平面电路来制造平面电路的方法。 本发明涉及将光刻掩模分为两部分,即主掩模和一个或多个从属掩模。 主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。 特别地,主掩模用作模板以提供用于平面电路的总体布局,而每个从屏蔽被改变以调谐和/或定制平面电路。 由于只有一小部分平面电路被重新设计和/或重写为新的掩模(即,从属掩模),本发明提供了一种用于优化平面电路的简单且成本有效的方法。 此外,由于大多数掩模错误将源自主掩模,本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。