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1. 发明授权

US07261982B2 Planar circuit optimization 有权
标题翻译：平面电路优化
公开(公告)号：US07261982B2
公开(公告)日：2007-08-28
申请号：US10736295
申请日：2003-12-15
申请人： Barthelemy Fondeur , Anca L. Sala , Robert J. Brainard , David K. Nakamoto , Tom Truong , Sanjay M. Thekdi , Anantharaman Vaidyanathan
发明人： Barthelemy Fondeur , Anca L. Sala , Robert J. Brainard , David K. Nakamoto , Tom Truong , Sanjay M. Thekdi , Anantharaman Vaidyanathan
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F7/70466 , G03F1/50 , G03F1/70
摘要： The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.
摘要翻译：本申请涉及使用光刻掩模组，光刻掩模组以及用光刻掩模组制造的平面电路制造平面电路的方法。本发明涉及将光刻掩模分为两部分，即主掩模和一个或多个从属掩模。主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。特别地，主掩模用作模板以提供用于平面电路的总体布局，而每个从屏蔽被改变以调谐和/或定制平面电路。由于只有一小部分平面电路被重新设计和/或重写为新的掩模（即，从属掩模），本发明提供了一种用于优化平面电路的简单且成本有效的方法。此外，由于大多数掩模错误将源自主掩模，本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。

2. 发明申请

US20130120891A1 Systems and Methods of Over-Load Protection with Voltage Fold-Back 有权
标题翻译：具有电压折返功能的过载保护系统和方法
公开(公告)号：US20130120891A1
公开(公告)日：2013-05-16
申请号：US13295638
申请日：2011-11-14
申请人： Tom Truong , John Vogt
发明人： Tom Truong , John Vogt
IPC分类号： H02H9/08
CPC分类号： H02M1/32 , H02M3/158 , H02M2001/0025
摘要： In a typical DC-DC converter, an error amplifier is used to sense and amplify the difference between the feedback voltage and the reference voltage. In the event of current overloading (limit condition), example embodiments of the disclosed systems and methods of over-load protection with voltage fold-back fold back the reference voltage proportional to the current limit. The regulator may continue to regulate in this fold-back voltage reference condition without shutting down the converter, saturating the inductor, or causing a catastrophic failure at the power FETs. The disclosed systems and methods of over-load protection with voltage fold-back resolve consecutive switching cycle current build up in high input voltage DC/DC convertor applications due to the latency of current limit circuitry.
摘要翻译：在典型的DC-DC转换器中，误差放大器用于检测和放大反馈电压和参考电压之间的差异。在当前超载（限制条件）的情况下，所公开的系统的示例实施例和具有电压折叠的过载保护方法将与电流限制成比例的参考电压折回。调节器可以在该折回电压参考条件下继续调节，而不关闭转换器，饱和电感器或在功率FET引起灾难性故障。所公开的具有电压折叠的过载保护的系统和方法由于电流限制电路的等待时间而在高输入电压DC / DC转换器应用中建立，从而解决连续的开关周期电流。

3. 发明申请

US20050031968A1 Planar circuit optimization 有权
标题翻译：平面电路优化
公开(公告)号：US20050031968A1
公开(公告)日：2005-02-10
申请号：US10736295
申请日：2003-12-15
申请人： Barthelemy Fondeur , Anca Sala , Robert Brainard , David Nakamoto , Tom Truong , Sanjay Thekdi , Anantharaman Vaidyanathan
发明人： Barthelemy Fondeur , Anca Sala , Robert Brainard , David Nakamoto , Tom Truong , Sanjay Thekdi , Anantharaman Vaidyanathan
IPC分类号： G03C5/00 , G03F1/14 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70466 , G03F1/50 , G03F1/70
摘要： The present application relates to a method of fabricating planar circuits using a photolithographic mask set, to the photolithographic mask set, and to a planar circuit fabricated with the photolithographic mask set. The instant invention involves separating a photolithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photolithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.
摘要翻译：本申请涉及使用光刻掩模组，光刻掩模组以及用光刻掩模组制造的平面电路来制造平面电路的方法。本发明涉及将光刻掩模分为两部分，即主掩模和一个或多个从属掩模。主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。特别地，主掩模用作模板以提供用于平面电路的总体布局，而每个从屏蔽被改变以调谐和/或定制平面电路。由于只有一小部分平面电路被重新设计和/或重写为新的掩模（即，从属掩模），本发明提供了一种用于优化平面电路的简单且成本有效的方法。此外，由于大多数掩模错误将源自主掩模，本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。

4. 发明授权

US09680365B2 Systems and methods of over-load protection with voltage fold-back 有权
公开(公告)号：US09680365B2
公开(公告)日：2017-06-13
申请号：US13295638
申请日：2011-11-14
申请人： Tom Truong , John Vogt
发明人： Tom Truong , John Vogt
IPC分类号： H02H3/08 , H02M1/32 , H02M3/158 , H02M1/00
CPC分类号： H02M1/32 , H02M3/158 , H02M2001/0025
摘要： In a typical DC-DC converter, an error amplifier is used to sense and amplify the difference between the feedback voltage and the reference voltage. In the event of current overloading (limit condition), example embodiments of the disclosed systems and methods of over-load protection with voltage fold-back fold back the reference voltage proportional to the current limit. The regulator may continue to regulate in this fold-back voltage reference condition without shutting down the converter, saturating the inductor, or causing a catastrophic failure at the power FETs. The disclosed systems and methods of over-load protection with voltage fold-back resolve consecutive switching cycle current build up in high input voltage DC/DC convertor applications due to the latency of current limit circuitry.

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