专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060225020A1 Methods and apparatus for 3-D FPGA design 审中-公开
标题翻译： 3-D FPGA设计方法与装置
公开(公告)号：US20060225020A1
公开(公告)日：2006-10-05
申请号：US11097363
申请日：2005-04-01
申请人： Anantha Chandrakasan , Young-Su Kwon , Payam Lajevardi , Francis Honore , L. Reif , Donald Troxel
发明人： Anantha Chandrakasan , Young-Su Kwon , Payam Lajevardi , Francis Honore , L. Reif , Donald Troxel
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , H03K19/17784 , H03K19/17796
摘要： Methods, apparatus, and systems are directed to an FPGA that includes a three-dimensional architecture having a component coupled to at least five components across two or more strata. In one embodiment, a FPGA includes a three dimensional switch that can be coupled to at least the five switches, wherein switches are located on first and second stratum. In another embodiment, slice instances are placed in inter-stratum and intra-stratum stages.
摘要翻译：方法，装置和系统涉及包括三维架构的FPGA，其具有耦合到两个或更多个层上的至少五个组件的组件。在一个实施例中，FPGA包括可以耦合到至少五个开关的三维开关，其中开关位于第一和第二层上。在另一个实施例中，切片实例被放置在层间和层内阶段。

2. 发明申请

US20100270996A1 CIRCUIT AND METHOD TO STARTUP FROM VERY LOW VOLTAGES AND IMPROVE ENERGY HARVESTING EFFICIENCY IN THERMOELECTRIC HARVESTERS 有权
标题翻译：从非常低的电压启动的电路和方法，并提高热电收割机的能源收集效率
公开(公告)号：US20100270996A1
公开(公告)日：2010-10-28
申请号：US12577421
申请日：2009-10-12
申请人： Yogesh Ramadas , Anantha Chandrakasan
发明人： Yogesh Ramadas , Anantha Chandrakasan
IPC分类号： G05F3/08
CPC分类号： H02M1/36
摘要： An energy harvesting system is provided that includes a startup module for starting the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to trigger a switch which permits the startup module to charge one or more first capacitive elements so to as reach a first defined voltage. A storage module buffers energy obtained from a thermoelectric harvester to be used by a load device. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. A DC-DC converter module provides regulated voltage to the load device after energy has been transferred from the thermoelectric harvester. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device.
摘要翻译：提供能量收集系统，其包括用于从完全关闭状态启动能量收集系统操作的启动模块。启动模块由于运动而使用机械振动来触发开关，其允许启动模块对一个或多个第一电容元件充电以便达到第一限定电压。存储模块缓冲由热收缩机获得的能量，由负载装置使用。当达到第一限定电压时，存储模块开始存储来自热电收集器的能量，允许一个或多个第二电容元件的充电达到第二限定电压。 DC-DC转换器模块在从热电收集器转移能量之后向负载装置提供调节电压。 DC-DC转换器模块确定是否已经达到第二定义电压，并释放一个或多个第一电容元件和负载装置中的存储能量。

3. 发明申请

US20100079034A1 CIRCUIT AND METHOD TO IMPROVE ENERGY HARVESTING EFFICIENCY IN PIEZOELECTRIC HARVESTERS 有权
标题翻译：提高压电式收割机能源收集效率的电路及方法
公开(公告)号：US20100079034A1
公开(公告)日：2010-04-01
申请号：US12558820
申请日：2009-09-14
申请人： Yogesh Ramadass , Anantha Chandrakasan
发明人： Yogesh Ramadass , Anantha Chandrakasan
IPC分类号： H01L41/107
CPC分类号： H02N2/181
摘要： An energy harvester circuit is provided. The energy harvester circuit includes a harvesting module for extracting energy from an ambient source. A bias flip module manages the manner in which voltage across the harvesting module transitions when input current from the harvesting module changes direction so as to allow a majority of the charge available from the harvesting module to be extracted. A voltage transitioning module is shared amongst one or more DC-DC converters for efficient energy management.
摘要翻译：提供能量采集电路。能量收集器电路包括用于从环境源提取能量的收集模块。偏置翻转模块管理当来自收获模块的输入电流改变方向时收集模块上的电压转变的方式，以便允许从采集模块获得的大部分电荷被提取。电压转换模块在一个或多个DC-DC转换器之间共享以实现有效的能量管理。

4. 发明授权

US5790269A Method and apparatus for compressing and decompressing a video image 失效
标题翻译：用于压缩和解压缩视频图像的方法和装置
公开(公告)号：US5790269A
公开(公告)日：1998-08-04
申请号：US570765
申请日：1995-12-12
申请人： Ichiro Masaki , Ujjaval Desai , Anantha Chandrakasan , Berthold Horn
发明人： Ichiro Masaki , Ujjaval Desai , Anantha Chandrakasan , Berthold Horn
IPC分类号： G06T9/20 , H04N7/26 , H04N1/40
CPC分类号： G06T9/20 , H04N19/20
摘要： Edge or contour information is extracted from an image array by filtering and encoded. In order to improve reproduction accuracy, two separate filters are used to detect edge information. One of the filters detects "sharp" edges, or edges in which the discontinuity in pixel intensity values occurs over a range of a few pixels. The other filter detects "level" edges in which the pixel intensity value discontinuity occurs over a larger range of pixels than the "sharp" edges. The "smooth" areas between edges or contours are assumed to vary continuously between the contours, but for efficient implementation, a one-dimensional linear interpolation is used to regenerate the contour information between edges. In addition, to further improve performance, a line is fitted to the pixel intensity data. The end values of this line are then used for the pixel intensity data. In order to still further improve performance, the pixel intensity values associated with each contour are divided into groups and each group is then encoded. Another improvement is accomplished by mean coding the residual error.
摘要翻译：通过滤波和编码从图像阵列中提取边缘或轮廓信息。为了提高再现精度，使用两个单独的滤波器来检测边缘信息。其中一个滤波器检测“锐利”边缘，或者在几个像素范围内发生像素强度值不连续性的边缘。另一个滤波器检测到像素强度值不连续发生在比“锐利”边缘更大的像素范围内的“电平”边缘。假设边缘或轮廓之间的“平滑”区域在轮廓之间连续变化，但是为了有效实现，使用一维线性内插来重新生成边缘之间的轮廓信息。此外，为了进一步提高性能，将线条拟合到像素强度数据。然后将该行的结束值用于像素强度数据。为了进一步提高性能，将与每个轮廓相关联的像素强度值分成组，然后对每个组进行编码。另一个改进是通过平均编码残差来实现的。

5. 发明授权

US09313072B2 Integrated circuit implementation of methods and apparatuses for monitoring occupancy of wideband GHz spectrum, and sensing respective frequency components of time-varying signals using sub-nyquist criterion signal sampling 有权
标题翻译：用于监视宽带GHz频谱占用的方法和装置的集成电路实现，以及使用次奎斯特准则信号采样来感测时变信号的各个频率分量
公开(公告)号：US09313072B2
公开(公告)日：2016-04-12
申请号：US14548238
申请日：2014-11-19
申请人： Dina Katabi , Omid Salehi-Abari , Ezzeldin Hamed , Haitham Z. Al-Hassanieh , Lixin Shi , Abhinav Agarwal , Anantha Chandrakasan , Vladimir Stojanovic
发明人： Dina Katabi , Omid Salehi-Abari , Ezzeldin Hamed , Haitham Z. Al-Hassanieh , Lixin Shi , Abhinav Agarwal , Anantha Chandrakasan , Vladimir Stojanovic
IPC分类号： H04L27/26 , H04B1/40 , H04L27/00 , H04L25/03 , G01P3/489
CPC分类号： H04L25/024 , G01P3/489 , H04B1/16 , H04B1/40 , H04L25/03038 , H04L27/0006 , H04L27/263 , H04L27/265 , H04L27/2666 , H04W16/14
摘要： An ASIC for monitoring wideband GHz spectrum to sense respective frequency components present in the spectrum. The ASIC implements Fast Fourier Transform (FFT) techniques to facilitate identification of one or more frequency components of a sparse signal after the signal is sub-sampled at a rate below the Nyquist criterion. The ASIC computes a first Fast Fourier Transform (FFT) of a first sub-sampled set of samples of a time-varying signal representing the monitored spectrum and sampled at a first sampling rate, and further computes a second FFT of a second sub-sampled set of samples of the time-varying signal sampled at a second sampling rate different from the first sampling rate. In one example, each of the first FFT and the second FFT is a low-radix FFT to facilitate a low-power and low-cost ASIC implementation of wideband spectrum sensing.
摘要翻译：用于监测宽带GHz频谱以检测频谱中存在的相应频率分量的ASIC。在以低于奈奎斯特准则的速率对信号进行子采样之后，ASIC实现快速傅立叶变换（FFT）技术以便于识别稀疏信号的一个或多个频率分量。 ASIC计算表示所监视的频谱并以第一采样率采样的时变信号的第一子采样采样集合的第一快速傅立叶变换（FFT），并且还计算第二次采样的第二FFT 以与第一采样率不同的第二采样率采样的时变信号的采样集合。在一个示例中，第一FFT和第二FFT中的每一个是低基FFT，以促进宽带频谱感测的低功率和低成本ASIC实施。

6. 发明授权

US06967522B2 Adaptive power supply and substrate control for ultra low power digital processors using triple well control 有权
标题翻译：使用三重控制的超低功耗数字处理器的自适应电源和基板控制
公开(公告)号：US06967522B2
公开(公告)日：2005-11-22
申请号：US10115307
申请日：2002-04-03
申请人： Anantha Chandrakasan , Masayuki Miyazaki , James Kao
发明人： Anantha Chandrakasan , Masayuki Miyazaki , James Kao
IPC分类号： G05F3/20 , G05F3/02
CPC分类号： G05F3/205
摘要： A system for improving the power efficiency of an electronic device includes a threshold voltage selector and a supply voltage selector. The threshold voltage selector selects a value of a threshold voltage for operation of the device in response to a present operating condition of the device. The supply voltage selector selects a value of a supply voltage to be applied to the device in response to the present operating condition of the device. The value of the threshold voltage and the value of the supply voltage control a power consumption of the device.
摘要翻译：一种用于提高电子设备的功率效率的系统包括阈值电压选择器和电源电压选择器。阈值电压选择器响应于设备的当前操作条件选择用于设备操作的阈值电压值。电源电压选择器响应于设备的当前操作条件选择要施加到设备的电源电压的值。阈值电压值和电源电压值控制器件的功耗。

7. 发明授权

US06661860B1 Multiple arbiter jitter estimation system and related techniques 失效
标题翻译：多仲裁抖动估计系统及相关技术
公开(公告)号：US06661860B1
公开(公告)日：2003-12-09
申请号：US09478106
申请日：2000-01-04
申请人： Vadim Gutnik , Anantha Chandrakasan
发明人： Vadim Gutnik , Anantha Chandrakasan
IPC分类号： H04L700
CPC分类号： H04L1/205 , G01R29/26
摘要： A digital circuit includes a plurality of arbiters, each arbiter having first and second input ports and an output port at which is provided an arbiter output signal. Each first input of the plurality of arbiters is connected to a first common line and each second input of the plurality of arbiters is connected to a second common line. The digital circuit further includes a decision circuit, having a plurality of inputs and an output, with each of the inputs of the decision circuit coupled to a corresponding one of the output of the plurality of arbiters. The decision circuit provides an output signal indicative of the time difference between a signal fed to the first common line and a signal fed to the second common line. With such an arrangement, phase jitter or timing jitter in a clock network can be measured with relatively high resolution and the system cam resolve cycle-by-cycle jitter with a predetermined resolution.
摘要翻译：数字电路包括多个仲裁器，每个仲裁器具有第一和第二输入端口以及输出端口，在该输出端口提供仲裁器输出信号。多个仲裁器的每个第一输入连接到第一公共线，并且多个仲裁器的每个第二输入连接到第二公共线。数字电路还包括具有多个输入和输出的判定电路，其中判决电路的每个输入耦合到多个仲裁器的输出中的对应的一个。判定电路提供指示馈送到第一公共线的信号和馈送到第二公共线的信号之间的时间差的输出信号。通过这样的布置，可以以相对高的分辨率测量时钟网络中的相位抖动或定时抖动，并且系统凸轮以预定分辨率解决逐周期抖动。

8. 发明授权

US09608652B2 Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters 有权
公开(公告)号：US09608652B2
公开(公告)日：2017-03-28
申请号：US14948875
申请日：2015-11-23
申请人： Sunghyuk Lee , Hae-Seung Lee , Anantha Chandrakasan
发明人： Sunghyuk Lee , Hae-Seung Lee , Anantha Chandrakasan
IPC分类号： H03M1/06 , H03M1/08 , H03M1/00 , H03M1/18 , H03M1/46 , H03M1/12
CPC分类号： H03M1/0609 , H03M1/002 , H03M1/0836 , H03M1/121 , H03M1/1215 , H03M1/123 , H03M1/1245 , H03M1/181 , H03M1/46
摘要： A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

9. 发明申请

US20160079994A1 METHODS AND APPARATUS FOR REDUCING TIMING-SKEW ERRORS IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：用于减少时间间隔异或模数转换器中的时序误差的方法和装置
公开(公告)号：US20160079994A1
公开(公告)日：2016-03-17
申请号：US14948875
申请日：2015-11-23
申请人： Sunghyuk Lee , Hae-Seung Lee , Anantha Chandrakasan
发明人： Sunghyuk Lee , Hae-Seung Lee , Anantha Chandrakasan
IPC分类号： H03M1/06 , H03M1/18 , H03M1/46 , H03M1/00 , H03M1/12
CPC分类号： H03M1/0609 , H03M1/002 , H03M1/0836 , H03M1/121 , H03M1/1215 , H03M1/123 , H03M1/1245 , H03M1/181 , H03M1/46
摘要： A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.
摘要翻译：时间交织（TI）模数转换器（ADC）架构采用低分辨率粗ADC通道，以奈奎斯特速率对输入模拟信号进行采样，便于定时偏移误差的背景校准，而不会中断对采样/ 转换输入信号。粗ADC通道为多个更高分辨率TI ADC通道提供了时序参考，分别以较低的采样率采样输入信号。将粗ADC数字输出与相应的TI ADC数字输出进行比较，可随时调整TI ADC通道的相应采样时钟，使其与粗ADC通道的采样时钟基本对齐，从而减少定时偏移误差。在一个示例中，粗ADC输出提供相应TI ADC数字输出的最高有效位（MSB），以进一步提高转换速度并降低这些通道的功耗。

10. 发明授权

US07400276B1 Method and apparatus for reducing delay in a bus provided from parallel, capacitively coupled transmission lines 有权
标题翻译：用于减少从并联的电容耦合传输线路提供的总线延迟的方法和装置
公开(公告)号：US07400276B1
公开(公告)日：2008-07-15
申请号：US10351811
申请日：2003-01-27
申请人： Paul P. Sotiriadis , Anantha Chandrakasan
发明人： Paul P. Sotiriadis , Anantha Chandrakasan
IPC分类号： H03M7/00
CPC分类号： H03M5/14 , H03M5/145
摘要： A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to restrict a number of possible transitions on the bus to a number that is smaller than the maximum number of possible transitions so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted.
摘要翻译：一种用于由并联的电容耦合总线提供的总线的机制，用于将总线上的可能的转换数量限制在小于最大可能跳变数量的数量，使得总线上的数据传输发生在传输如果没有限制转换次数，则该速率高于允许的传输速率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式