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1. 发明申请

US20060225020A1 Methods and apparatus for 3-D FPGA design 审中-公开
标题翻译： 3-D FPGA设计方法与装置
公开(公告)号：US20060225020A1
公开(公告)日：2006-10-05
申请号：US11097363
申请日：2005-04-01
申请人： Anantha Chandrakasan , Young-Su Kwon , Payam Lajevardi , Francis Honore , L. Reif , Donald Troxel
发明人： Anantha Chandrakasan , Young-Su Kwon , Payam Lajevardi , Francis Honore , L. Reif , Donald Troxel
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , H03K19/17784 , H03K19/17796
摘要： Methods, apparatus, and systems are directed to an FPGA that includes a three-dimensional architecture having a component coupled to at least five components across two or more strata. In one embodiment, a FPGA includes a three dimensional switch that can be coupled to at least the five switches, wherein switches are located on first and second stratum. In another embodiment, slice instances are placed in inter-stratum and intra-stratum stages.
摘要翻译：方法，装置和系统涉及包括三维架构的FPGA，其具有耦合到两个或更多个层上的至少五个组件的组件。在一个实施例中，FPGA包括可以耦合到至少五个开关的三维开关，其中开关位于第一和第二层上。在另一个实施例中，切片实例被放置在层间和层内阶段。

2. 发明申请

US20080126758A1 Digital signal processing apparatus and method for multiply-and-accumulate operation 审中-公开
标题翻译：用于乘法和累加操作的数字信号处理装置和方法
公开(公告)号：US20080126758A1
公开(公告)日：2008-05-29
申请号：US11644724
申请日：2006-12-22
申请人： Young-Su Kwon , Bon-Tae Koo , Nak-Woong Eum
发明人： Young-Su Kwon , Bon-Tae Koo , Nak-Woong Eum
IPC分类号： G06F9/302
CPC分类号： G06F9/3001
摘要： A digital signal processing apparatus and method for MAC operation are disclosed. The DSP apparatus including: a first memory for storing a plurality of first operands; a second memory for storing a plurality of second operands; a MAC processor including a plurality of parallel MAC blocks disposed in parallel for performing a parallel MAC operation on a first operand outputted from the first memory in parallel and a second operand outputted from the second memory in parallel using the parallel MAC blocks, wherein the first memory and the second memory include dual port memories for outputting the plurality of the first operands and the second operands to the plurality of parallel MAC blocks in parallel.
摘要翻译：公开了一种用于MAC操作的数字信号处理装置和方法。 DSP装置包括：第一存储器，用于存储多个第一操作数; 用于存储多个第二操作数的第二存储器; MAC处理器，包括并行设置的多个并行MAC块，用于对从第一存储器并行输出的第一操作数并行地执行并行MAC操作，以及使用并行MAC块并行地从第二存储器输出的第二操作数，其中第一存储器和第二存储器包括用于并行地将多个第一操作数和第二操作数输出到多个并行MAC块的双端口存储器。

3. 发明授权

US09274794B2 Processor and instruction processing method in processor 有权
标题翻译：处理器处理器和指令处理方法
公开(公告)号：US09274794B2
公开(公告)日：2016-03-01
申请号：US13608774
申请日：2012-09-10
申请人： Young-Su Kwon
发明人： Young-Su Kwon
IPC分类号： G06F9/00 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30076 , G06F9/328 , G06F9/3802 , G06F9/3808 , G06F9/3844
摘要： The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache.
摘要翻译：处理器技术领域本发明涉及一种处理器，包括：指令高速缓存，被配置为存储存储在外部存储器中的第一指令中的至少一些以及每个包括多个微指令的第二指令; 配置为存储与包括在第二指令中的多个微指令相对应的第三指令的微缓存器; 以及核心，被配置为从指令高速缓存读出第一和第二指令，并执行计算，其中核心在正常模式下执行来自指令高速缓存的第一指令的计算，并且当处理进入微指令模式时，核心通过与从微缓存器提供的多个微指令相对应的第三指令执行计算。

4. 发明授权

US08464006B2 Method and apparatus for data transmission between processors using memory remapping 有权
标题翻译：使用存储器重映射的处理器之间的数据传输的方法和装置
公开(公告)号：US08464006B2
公开(公告)日：2013-06-11
申请号：US12027364
申请日：2008-02-07
申请人： Young-Su Kwon , Hyuk Kim , Young-Seok Baek , Suk Ho Lee , Bon Tae Koo , Nak Woong Eum
发明人： Young-Su Kwon , Hyuk Kim , Young-Seok Baek , Suk Ho Lee , Bon Tae Koo , Nak Woong Eum
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1072
摘要： Provided are a method and apparatus for efficiently transferring a massive amount of multimedia data between two processors. The apparatus includes a first local switch, which connects a virtual page of a first processor element to a shared memory page, a second local switch, which connects a virtual page of a second processor element to the shared memory page, a shared page switch, which connects a predetermined shared memory page of a shared physical memory to the first or second local switch, and a switch manager, which remaps a certain shared memory page of the shared physical memory that stores data of a task performed by the first processor element to the virtual page of the second processor element. Accordingly, since memory remapping is used, the massive amount of multimedia data can be transmitted by changing a method of mapping a memory, unlike a case when multimedia data is transmitted by using a memory bus.
摘要翻译：提供了一种用于在两个处理器之间有效地传送大量多媒体数据的方法和装置。该设备包括将第一处理器元件的虚拟页面连接到共享存储器页面的第一本地开关，将第二处理器元件的虚拟页面连接到共享存储器页面的第二本地开关，共享页面开关，其将共享物理存储器的预定共享存储器页面连接到第一或第二本地交换机，以及交换机管理器，其将存储由第一处理器元件执行的任务的数据的共享物理存储器的某个共享存储器页重新映射到第二处理器元件的虚拟页面。因此，由于使用存储器重映射，与通过使用存储器总线发送多媒体数据的情况不同，可以通过改变映射存储器的方法来发送大量的多媒体数据。

5. 发明申请

US20120117357A1 ENERGY TILE PROCESSOR 审中-公开
标题翻译：能源处理器
公开(公告)号：US20120117357A1
公开(公告)日：2012-05-10
申请号：US13280370
申请日：2011-10-25
申请人： Young-Su Kwon
发明人： Young-Su Kwon
IPC分类号： G06F15/78 , G06F9/312 , G06F9/30
CPC分类号： G06F9/4893 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： An energy tile processor in which an internal structure of a single processor is divided into a part for supplying instructions and another part for executing the instructions in order for operating voltages and operating frequencies to be supplied independently. The processor includes an instruction supply unit storing instructions and issuing instructions to be executed, a first execution unit executing an integer operation and a memory operation according to an operation type of the instruction issued by the instruction supply unit, and a second execution unit executing a floating point operation according to an operation type of the instruction issued by the instruction supply unit. The instruction supply unit, the first execution unit, and the second execution unit are driven at operating voltages and operating frequencies which are independently controlled.
摘要翻译：一种能量瓦片处理器，其中单个处理器的内部结构被分成用于提供指令的部分和用于执行指令的另一部分，以便独立提供工作电压和工作频率。处理器包括指令提供单元，存储指令和发出要执行的指令，第一执行单元根据由指令提供单元发出的指令的操作类型执行整数操作和存储器操作，第二执行单元执行根据指令提供单元发出的指令的操作类型进行浮点运算。指令供给单元，第一执行单元和第二执行单元以独立控制的工作电压和工作频率被驱动。

6. 发明授权

US07900018B2 Embedded system and page relocation method therefor 有权
标题翻译：嵌入式系统和页面重定位方法
公开(公告)号：US07900018B2
公开(公告)日：2011-03-01
申请号：US11949879
申请日：2007-12-04
申请人： Young-Su Kwon , Bon-Tae Koo , Nak-Woong Eum
发明人： Young-Su Kwon , Bon-Tae Koo , Nak-Woong Eum
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3287 , G06F12/023 , G06F12/0292 , G06F12/06 , Y02D10/14 , Y02D10/171
摘要： Provided are an embedded system and a method for relocating memory pages therefor. The embedded system includes a processor, a data relocating circuit for receiving a logical address from the processor, mapping the received logical address to a physical address to locate a valid page in a predetermined bank, and generating a bank power control signal according to whether or not a corresponding memory bank includes valid pages, and a memory including a plurality of memory banks addressed by a physical address outputted from the data relocating circuit and a plurality of switching means for selectively supplying a power voltage to each of memory banks in response to the bank power control signal.
摘要翻译：提供了一种用于重新定位其存储器页面的嵌入式系统和方法。嵌入式系统包括处理器，用于从处理器接收逻辑地址的数据重新定位电路，将接收到的逻辑地址映射到物理地址以定位预定存储体中的有效页面，以及根据是否或者不是相应的存储体包括有效页面，以及存储器，其包括由数据重定位电路输出的物理地址寻址的多个存储器组，以及多个开关装置，用于响应于该存储器选择性地向每个存储体提供电源电压银行电源控制信号。

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