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1. 发明授权

US06967522B2 Adaptive power supply and substrate control for ultra low power digital processors using triple well control 有权
标题翻译：使用三重控制的超低功耗数字处理器的自适应电源和基板控制
公开(公告)号：US06967522B2
公开(公告)日：2005-11-22
申请号：US10115307
申请日：2002-04-03
申请人： Anantha Chandrakasan , Masayuki Miyazaki , James Kao
发明人： Anantha Chandrakasan , Masayuki Miyazaki , James Kao
IPC分类号： G05F3/20 , G05F3/02
CPC分类号： G05F3/205
摘要： A system for improving the power efficiency of an electronic device includes a threshold voltage selector and a supply voltage selector. The threshold voltage selector selects a value of a threshold voltage for operation of the device in response to a present operating condition of the device. The supply voltage selector selects a value of a supply voltage to be applied to the device in response to the present operating condition of the device. The value of the threshold voltage and the value of the supply voltage control a power consumption of the device.
摘要翻译：一种用于提高电子设备的功率效率的系统包括阈值电压选择器和电源电压选择器。阈值电压选择器响应于设备的当前操作条件选择用于设备操作的阈值电压值。电源电压选择器响应于设备的当前操作条件选择要施加到设备的电源电压的值。阈值电压值和电源电压值控制器件的功耗。

2. 发明申请

US20070075786A1 Suppressing noise in a frequency synthesizer 审中-公开
标题翻译：抑制频率合成器中的噪声
公开(公告)号：US20070075786A1
公开(公告)日：2007-04-05
申请号：US11473993
申请日：2006-06-23
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03L7/00
CPC分类号： H03L7/0896 , H03L7/0893 , H03L7/18 , H03L7/193
摘要： A frequency synthesizer includes analog components and digital components. The frequency synthesizer includes at least one shunt regulator that is coupled to a supply rail to provide power to at least one of the digital components. The frequency synthesizer also includes at least one series regulator that is coupled to the supply rail to provide power to at least one of the analog components.
摘要翻译：频率合成器包括模拟组件和数字组件。频率合成器包括至少一个并联稳压器，其耦合到电源轨以向至少一个数字组件提供功率。频率合成器还包括耦合到电源轨的至少一个串联调节器，以向至少一个模拟组件供电。

3. 发明申请

US20060139105A1 Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques 有权
公开(公告)号：US20060139105A1
公开(公告)日：2006-06-29
申请号：US11023981
申请日：2004-12-28
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/0893 , H03L7/0898 , H03L7/0995 , H03L7/18 , H03L2207/04
摘要： Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

4. 发明申请

US20070075793A1 Providing a low phase noise reference clock signal 审中-公开
标题翻译：提供低相位噪声参考时钟信号
公开(公告)号：US20070075793A1
公开(公告)日：2007-04-05
申请号：US11473742
申请日：2006-06-23
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03B1/00
CPC分类号： H03L7/0895
摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.
摘要翻译：参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。整形电路整形周期信号以产生时钟信号。滤波器位于振荡器和整形电路之间。

5. 发明授权

US07599673B2 Receiver architectures utilizing coarse analog tuning and associated methods 失效
标题翻译：采用粗略模拟调谐和相关方法的接收机架构
公开(公告)号：US07599673B2
公开(公告)日：2009-10-06
申请号：US11240814
申请日：2005-09-30
申请人： Adrian Maxim , Ramin Khoini-Poorfard , James Kao
发明人： Adrian Maxim , Ramin Khoini-Poorfard , James Kao
IPC分类号： H04B1/18
CPC分类号： H04N7/20 , H03D3/006 , H03D3/007 , H03J1/0066 , H03K3/0322 , H03L7/18 , H04H40/90 , H04N5/4401 , H04N5/4446 , H04N5/50 , H04N21/4263
摘要： A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.
摘要翻译：一种技术包括在第一频率范围内接收包括多个信道的信号频谱。该技术包括接收标识要调谐的至少一个期望信道的选择信号。该技术包括提供具有与第一频率范围基本相同的第二频率范围的振荡器，并且控制振荡器以产生多个粗调模拟混合信号之一。信号基本跨越第二频率范围，并且每个信号取决于信号频谱内期望信道的位置。该技术包括将信号频谱与所选择的粗调模拟混合信号混合以产生粗调谐信号频谱。该技术包括对粗调谐信号频谱进行数字处理以微调所需信道并产生所需信道的数字基带信号。

6. 发明授权

US07095287B2 Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques 有权
标题翻译：使用开环校准技术实现过程，温度和分频器模数独立PLL环路带宽和阻尼因子的方法和装置
公开(公告)号：US07095287B2
公开(公告)日：2006-08-22
申请号：US11023981
申请日：2004-12-28
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03L7/06 , H03L7/08
CPC分类号： H03L7/093 , H03L7/0893 , H03L7/0898 , H03L7/0995 , H03L7/18 , H03L2207/04
摘要： Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.
摘要翻译：公开了针对环路带宽和阻尼因子提供过程，温度和分频器模数独立性的锁相环电路（PLL）的几种开环校准技术。介绍了两类开环技术。第一种方法仅使用来自振荡器的输出频率的单次测量，并调整执行环路带宽和阻尼因子同时校准的单个PLL环路元件。对于振荡器控制信号的给定值测量输出频率，并且调整电荷泵电流，使得其消除振荡器增益的过程变化。第二种方法使用两个单独的和正交的校准步骤，它们都基于当将已知的激励施加到开环信号路径时来自振荡器的输出频率的测量。在第一步中，通过在进入相位频率检测器的两个时钟之间施加恒定相移时，基于正向通路增益的测量来调整电荷泵电流，同时积分路径保持为恒定值。在第二步中，通过调整积分环路滤波电容器的值，通过调整积分环路滤波电容器的值，通过与积分电容器值成比例的电压激励时的振荡器输出频率的测量，同时比例控制分量为零，校准阻尼系数。

7. 发明申请

US20050226314A1 Communication devices capable of using system clock inputs for embedded television applications 有权
标题翻译：能够为嵌入式电视应用使用系统时钟输入的通信设备
公开(公告)号：US20050226314A1
公开(公告)日：2005-10-13
申请号：US10875863
申请日：2004-06-24
申请人： Shahram Tadayyon , James Nohrden , James Kao
发明人： Shahram Tadayyon , James Nohrden , James Kao
IPC分类号： H04B1/38 , H04L12/28
CPC分类号： H04L12/2801 , H04N21/4382 , H04N21/4383
摘要： According to one embodiment of the present invention, a device may receive one of multiple frequencies at a clock input of the device; determine which of the multiple frequencies is received; and generate at least one internal clock frequency for operation of the device using the received frequency. For example, such a device may be embedded within a system having a receiver to receive a satellite signal spectrum and to tune a signal channel and baseband circuitry coupled to the receiver to process digital data corresponding to the signal channel, where the baseband circuitry operates at the frequency provided to the device.
摘要翻译：根据本发明的一个实施例，设备可以在设备的时钟输入处接收多个频率中的一个; 确定接收多个频率中的哪一个; 并且使用接收到的频率生成至少一个内部时钟频率以用于设备的操作。例如，这样的设备可以嵌入在具有接收器的系统中，以接收卫星信号频谱并且调谐耦合到接收机的信号信道和基带电路以处理对应于信号信道的数字数据，其中基带电路在提供给设备的频率。

8. 发明申请

US20070006504A1 Picture frame having an inner frame movably received in an outer frame for exhibiting a planar drawing or a three dimensional object 失效
标题翻译：图像帧具有可移动地容纳在外框中的内框，用于展现平面图或三维物体
公开(公告)号：US20070006504A1
公开(公告)日：2007-01-11
申请号：US11451016
申请日：2006-06-12
申请人： James Kao
发明人： James Kao
IPC分类号： A47G1/06
CPC分类号： A47G1/12
摘要： A picture frame includes an outer frame having an extension slit defined in at least one side face of the outer frame and an inner frame movably received inside the outer frame. The inner frame has a first slit defined through at least one side face of the inner frame to correspond to and align with the extension slit of the outer frame for receiving therein a hollow frame, a second slit defined through at least one side face of the inner frame for receiving therein a picture and a third slit defined through at least one side face of the inner frame for receiving therein a background board.
摘要翻译：相框包括具有限定在外框的至少一个侧面中的延伸狭缝的外框和可移动地容纳在外框内的内框。内框架具有通过内框架的至少一个侧面限定的第一狭缝，以与外框架的延伸狭缝对应并与其对准，用于在其中容纳中空框架，第二狭缝通过至少一个侧面用于在其中容纳图像的内框架和通过内框架的至少一个侧面限定的第三狭缝，用于在其中接收背景板。

9. 发明授权

US07750704B2 Providing a low phase noise reference signal 失效
标题翻译：提供低相位噪声参考信号
公开(公告)号：US07750704B2
公开(公告)日：2010-07-06
申请号：US12256800
申请日：2008-10-23
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03K12/00
CPC分类号： H03L7/0895
摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.
摘要翻译：参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。整形电路整形周期信号以产生时钟信号。滤波器位于振荡器和整形电路之间。

10. 发明申请

US20090039935A1 Providing A Low Phase Noise Reference Signal 失效
标题翻译：提供低相位噪声参考信号
公开(公告)号：US20090039935A1
公开(公告)日：2009-02-12
申请号：US12256800
申请日：2008-10-23
申请人： Adrian Maxim , James Kao
发明人： Adrian Maxim , James Kao
IPC分类号： H03K12/00
CPC分类号： H03L7/0895
摘要： A reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit.
摘要翻译：参考时钟发生器包括用于产生周期信号的振荡器，整形电路和滤波器。整形电路整形周期信号以产生时钟信号。滤波器位于振荡器和整形电路之间。

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