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1. 发明申请

US20060049842A1 System and method for accurate negative bias temperature instability characterization 有权
标题翻译：准确的负偏压温度不稳定性表征的系统和方法
公开(公告)号：US20060049842A1
公开(公告)日：2006-03-09
申请号：US10935375
申请日：2004-09-07
申请人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
摘要翻译：提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。在测试期间，晶体管的漏极端子保持偏置电压。在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

2. 发明申请

US20060076971A1 System and method for accurate negative bias temperature instability characterization 有权
公开(公告)号：US20060076971A1
公开(公告)日：2006-04-13
申请号：US11290077
申请日：2005-11-30
申请人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

3. 发明授权

US07212023B2 System and method for accurate negative bias temperature instability characterization 有权
标题翻译：准确的负偏压温度不稳定性表征的系统和方法
公开(公告)号：US07212023B2
公开(公告)日：2007-05-01
申请号：US10935375
申请日：2004-09-07
申请人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
摘要翻译：提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。在测试期间，晶体管的漏极端子保持偏置电压。在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

4. 发明授权

US07218132B2 System and method for accurate negative bias temperature instability characterization 有权
公开(公告)号：US07218132B2
公开(公告)日：2007-05-15
申请号：US11290077
申请日：2005-11-30
申请人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
发明人： Anand T. Krishnan , Srikanth Krishnan , Vijay Reddy , Cathy Chancellor
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

5. 发明授权

US08404247B2 Antitoxin and vaccine platform based on nodavirus VLPS 失效
标题翻译：基于诺塔病毒VLPS的抗毒素和疫苗平台
公开(公告)号：US08404247B2
公开(公告)日：2013-03-26
申请号：US13167627
申请日：2011-06-23
申请人： John Young , Anette Schneemann , Marianne Manchester , Kelly Dryden , John M. Marlett , Darly Joseph Manayani , Godfrey Jonah Anderson Rainey , Vijay Reddy , Marc E. Siladi , Heather M. Scobie , Diane Thomas , Mark Yeager
发明人： John Young , Anette Schneemann , Marianne Manchester , Kelly Dryden , John M. Marlett , Darly Joseph Manayani , Godfrey Jonah Anderson Rainey , Vijay Reddy , Marc E. Siladi , Heather M. Scobie , Diane Thomas , Mark Yeager
IPC分类号： A61K39/385 , A61K39/07 , A61K39/08 , A61K39/116 , A61K39/295
CPC分类号： A61K39/07 , A61K2039/5256 , A61K2039/5258 , C12N2710/14143 , C12N2770/30023
摘要： Antitoxin and vaccine compositions based on nodavirus VLPs are provided. Anthrax antitoxin and vaccine compositions are provided. Methods of treating toxins with VLP-based antitoxins are provided. Methods of raising an immune response with immunogen decorated VLPs are provided.
摘要翻译：提供了基于转染病毒VLP的抗毒素和疫苗组合物。提供炭疽毒素抗毒素和疫苗组合物。提供了使用基于VLP的抗毒素治疗毒素的方法。提供了用免疫原装饰的VLP提高免疫应答的方法。

6. 发明申请

US20050280477A1 Versatile system for accelerated stress characterization of semiconductor device structures 有权
标题翻译：用于半导体器件结构加速应力表征的多功能系统
公开(公告)号：US20050280477A1
公开(公告)日：2005-12-22
申请号：US10871932
申请日：2004-06-18
申请人： Vijay Reddy , Prasun Raha
发明人： Vijay Reddy , Prasun Raha
IPC分类号： G01R31/27 , G01R31/28 , H03K3/03
CPC分类号： G01R31/2884 , G01R31/275 , G01R31/2856
摘要： The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.
摘要翻译：本发明提供一种用于执行给定晶体管（204）的加速应力表征的系统（200）。由给定晶体管形成的逆变器电路彼此串联设置（202）。多个信号抽头可操作地与相邻逆变器电路之间的每个间隙相关联。选择性电路可操作地耦合到多个信号抽头，并且适于从多个信号抽头中的第一和第二信号抽头输出（206）数据。受控电压分量（212）可操作地耦合多个逆变器电路，并且适于提供期望的电源电压。受控信号分量（210）可操作地耦合多个逆变器电路，并且适于向其提供期望频率的信号。评估组件（208）从第一和第二信号抽头接收用于评估或处理的信号数据。

7. 发明授权

US07263455B2 Apparatus and methods for ferroelectric ram fatigue testing 有权
标题翻译：铁电柱塞疲劳试验装置及方法
公开(公告)号：US07263455B2
公开(公告)日：2007-08-28
申请号：US11152318
申请日：2005-06-14
申请人： John Anthony Rodriguez , Vijay Reddy
发明人： John Anthony Rodriguez , Vijay Reddy
IPC分类号： H04L1/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.
摘要翻译：提供了用于在晶片中疲劳测试铁电材料的装置，其包括片上振荡器以向形成在晶片中的铁电电容器提供双极波形，以及用于选择性地提供对铁电电容器的外部访问的开关系统。还提供了测试方法，包括测量晶片中的铁电电容器的性能特性，使用片上振荡器向铁电电容器提供双极波形多个周期，并再次测量整数之后的性能特性的双极波形的周期。

8. 发明申请

US20050086038A1 Method and system for determining transistor degradation mechanisms 有权
公开(公告)号：US20050086038A1
公开(公告)日：2005-04-21
申请号：US10687796
申请日：2003-10-17
申请人： Vijay Reddy , Robert Pitts
发明人： Vijay Reddy , Robert Pitts
IPC分类号： G01R27/28 , G01R31/26 , G06F17/50 , H01L21/66 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34
摘要： According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay elements. Each delay element operates as a delay element through the use of one or more transistors of only a first type and no transistors of the opposite type. The method further includes operating the ring oscillator and measuring the frequency resulting from the ring oscillator over time. The magnitude of an isolated degradation mechanism is determined based on a comparison of the measured frequency and an expected frequency for the ring oscillator absent degradation.

9. 发明申请

US20050231997A1 Apparatus and methods for ferroelectric ram fatigue testing 有权
标题翻译：铁电柱塞疲劳试验装置及方法
公开(公告)号：US20050231997A1
公开(公告)日：2005-10-20
申请号：US11152318
申请日：2005-06-14
申请人： John Rodriguez , Vijay Reddy
发明人： John Rodriguez , Vijay Reddy
IPC分类号： G11C11/22 , G11C29/50 , H04L1/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Apparatus are disclosed for fatigue testing ferroelectric material in a wafer, comprising an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed, comprising measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.
摘要翻译：公开了用于疲劳测试晶片中的铁电材料的装置，其包括用于向形成在晶片中的铁电电容器提供双极波形的片上振荡器，以及用于选择性地提供对铁电电容器的外部访问的开关系统。还公开了测试方法，包括测量晶片中的铁电电容器的性能特征，使用片上振荡器向铁电电容器提供双极波形多个周期，并再次测量整数倍的双极波形的周期。

10. 发明申请

US20050218903A1 Voltage waveform generation circuit 审中-公开
标题翻译：电压波形发生电路
公开(公告)号：US20050218903A1
公开(公告)日：2005-10-06
申请号：US10814453
申请日：2004-03-31
申请人： Vijay Reddy , Prasun Raha
发明人： Vijay Reddy , Prasun Raha
IPC分类号： G01R31/08 , G01R31/319
CPC分类号： G01R31/31928 , G01R31/31924
摘要： A method and apparatus permit voltage waveforms to be generated based, in part, on a request containing a plurality of waveform parameters. The voltage waveforms preferably represents voltage overshoot or undershoots.
摘要翻译：一种方法和装置允许部分地基于包含多个波形参数的请求产生电压波形。电压波形优选地表示电压过冲或欠压。

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