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1. 发明申请

US20050140429A1 LOAD SENSING VOLTAGE REGULATOR FOR PLL/DLL ARCHITECTURES 有权
标题翻译： PLL / DLL结构的负载感应电压调节器
公开(公告)号：US20050140429A1
公开(公告)日：2005-06-30
申请号：US10749275
申请日：2003-12-29
申请人： T. Viswanathan , Prasun Raha
发明人： T. Viswanathan , Prasun Raha
IPC分类号： G05F1/10 , G05F1/46
CPC分类号： G05F1/465
摘要： An apparatus includes a voltage regulator operable to regulate a supply voltage to an on-chip module having an operational current, draw a supply current, and supply the operation current to the on-chip module. The supply current drawn by the voltage regulator is proportional to the operating current of the on-chip module.
摘要翻译：一种装置包括电压调节器，其可操作以调节具有工作电流的片上模块的电源电压，绘制电源电流，并将操作电流提供给片上模块。电压调节器提供的电源电流与片上模块的工作电流成比例。

2. 发明申请

US20050218903A1 Voltage waveform generation circuit 审中-公开
标题翻译：电压波形发生电路
公开(公告)号：US20050218903A1
公开(公告)日：2005-10-06
申请号：US10814453
申请日：2004-03-31
申请人： Vijay Reddy , Prasun Raha
发明人： Vijay Reddy , Prasun Raha
IPC分类号： G01R31/08 , G01R31/319
CPC分类号： G01R31/31928 , G01R31/31924
摘要： A method and apparatus permit voltage waveforms to be generated based, in part, on a request containing a plurality of waveform parameters. The voltage waveforms preferably represents voltage overshoot or undershoots.
摘要翻译：一种方法和装置允许部分地基于包含多个波形参数的请求产生电压波形。电压波形优选地表示电压过冲或欠压。

3. 发明申请

US20050117680A1 Frequency and phase correction in a phase-locked loop (PLL) 有权
标题翻译：锁相环（PLL）中的频率和相位校正
公开(公告)号：US20050117680A1
公开(公告)日：2005-06-02
申请号：US10725763
申请日：2003-12-02
申请人： Prasun Raha , T. Viswanathan , Richard Jennings
发明人： Prasun Raha , T. Viswanathan , Richard Jennings
IPC分类号： H03L7/089 , H03L7/093 , H03L7/099 , H03L7/107 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0893 , H03L7/093 , H03L7/0995 , H03L7/1072
摘要： In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summer, and a current-controlled oscillator (CCO). The phase frequency detector detects a frequency difference and a phase difference between a clock signal and a comparison signal, communicates the frequency difference to a first charge pump generating a first current, and communicates the phase difference to a second charge pump generating a voltage. The comparison signal is derived from an output signal of the PLL. The first charge pump modifies the first current according to the frequency difference and communicates the first current to the current summer. The second charge pump modifies the voltage according to the phase difference and communicates the voltage to the V2I converter. The V2I converter generates a second current corresponding to the voltage and communicates the second current to the current summer. The current summer combines the first and second currents with each other to generate a control current for the CCO and communicates the control current to the CCO. The CCO generates one or more oscillating signals according to the first and second currents. A frequency of an oscillating signal from the CCO changes in response to the modification of the first current, and a phase of the oscillating signal changes in response to the modification of the second current.
摘要翻译：在一个实施例中，用于锁相环（PLL）中的频率和相位校正的系统包括相位频率检测器，分别产生第一电流和电压的第一和第二电荷泵，电压 - 电流（V2I）转换器，当前夏天和电流控制振荡器（CCO）。相位频率检测器检测时钟信号和比较信号之间的频率差和相位差，将频差传送到产生第一电流的第一电荷泵，并将相位差传送到产生电压的第二电荷泵。比较信号从PLL的输出信号导出。第一个电荷泵根据频差改变第一个电流，并将第一个电流传送到当前夏天。第二个电荷泵根据相位差修改电压，并将电压传递给V2I转换器。 V2I转换器产生对应于电压的第二电流，并将第二电流传送到当前夏天。当前的夏天将第一和第二电流彼此相结合，以产生CCO的控制电流，并将控制电流传递给CCO。 CCO根据第一和第二电流产生一个或多个振荡信号。来自CCO的振荡信号的频率响应于第一电流的修改而改变，并且振荡信号的相位响应于第二电流的修改而改变。

4. 发明申请

US20050110579A1 Generating an oscillating signal according to a control current 有权
标题翻译：根据控制电流产生振荡信号
公开(公告)号：US20050110579A1
公开(公告)日：2005-05-26
申请号：US10722930
申请日：2003-11-25
申请人： Prasun Raha
发明人： Prasun Raha
IPC分类号： H03K3/03 , H03K3/354 , H03K5/00 , H03K5/12 , H03K5/13 , H03L7/089 , H03L7/099 , H03L7/00
CPC分类号： H03K3/0322 , H03K5/12 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L7/0893 , H03L7/0995
摘要： Generating an oscillating signal according to a control current includes receiving a control current corresponding to an oscillation frequency. A first differential signal and a second differential signal are generated by switching a first load according to the control current to yield the first differential signal, and switching a second load according to the control current to yield the second differential signal. The first load operates in opposition to the second load.
摘要翻译：根据控制电流产生振荡信号包括接收对应于振荡频率的控制电流。通过根据控制电流切换第一负载产生第一差分信号和第二差分信号以产生第一差分信号，并根据控制电流切换第二负载以产生第二差分信号。第一个负载与第二个负载相反。

5. 发明授权

US06847260B2 Low dropout monolithic linear regulator having wide operating load range 有权
标题翻译：低压差单片线性稳压器具有较宽的工作负载范围
公开(公告)号：US06847260B2
公开(公告)日：2005-01-25
申请号：US10422028
申请日：2003-04-23
申请人： Vishal I. Gupta , Prasun Raha , Gabriel A. Rincon-Mora
发明人： Vishal I. Gupta , Prasun Raha , Gabriel A. Rincon-Mora
IPC分类号： H03F1/08 , H03F3/45 , H03F1/14
CPC分类号： H03F1/086
摘要： A monolithic low dropout regulator includes an active capacitor multiplier that is used to form the dominant pole of the regulator, thereby yielding stability. This decouples the system stability from the high-frequency power supply rejection ratio (PSRR). The PSRR at high frequencies is tuned independently using a reasonable on-chip capacitor C2.
摘要翻译：单片低压差稳压器包括用于形成调节器的主极的有源电容乘法器，由此产生稳定性。这将系统稳定性与高频电源抑制比（PSRR）分离。使用合理的片上电容器C2独立调谐高频下的PSRR。

6. 发明申请

US20050280477A1 Versatile system for accelerated stress characterization of semiconductor device structures 有权
标题翻译：用于半导体器件结构加速应力表征的多功能系统
公开(公告)号：US20050280477A1
公开(公告)日：2005-12-22
申请号：US10871932
申请日：2004-06-18
申请人： Vijay Reddy , Prasun Raha
发明人： Vijay Reddy , Prasun Raha
IPC分类号： G01R31/27 , G01R31/28 , H03K3/03
CPC分类号： G01R31/2884 , G01R31/275 , G01R31/2856
摘要： The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.
摘要翻译：本发明提供一种用于执行给定晶体管（204）的加速应力表征的系统（200）。由给定晶体管形成的逆变器电路彼此串联设置（202）。多个信号抽头可操作地与相邻逆变器电路之间的每个间隙相关联。选择性电路可操作地耦合到多个信号抽头，并且适于从多个信号抽头中的第一和第二信号抽头输出（206）数据。受控电压分量（212）可操作地耦合多个逆变器电路，并且适于提供期望的电源电压。受控信号分量（210）可操作地耦合多个逆变器电路，并且适于向其提供期望频率的信号。评估组件（208）从第一和第二信号抽头接收用于评估或处理的信号数据。

7. 发明授权

US07026838B2 Versatile system for accelerated stress characterization of semiconductor device structures 有权
标题翻译：用于半导体器件结构加速应力表征的多功能系统
公开(公告)号：US07026838B2
公开(公告)日：2006-04-11
申请号：US10871932
申请日：2004-06-18
申请人： Vijay Kumar Reddy , Prasun Raha
发明人： Vijay Kumar Reddy , Prasun Raha
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/275 , G01R31/2856
摘要： The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.
摘要翻译：本发明提供一种用于执行给定晶体管（204）的加速应力表征的系统（200）。由给定晶体管形成的逆变器电路彼此串联设置（202）。多个信号抽头可操作地与相邻逆变器电路之间的每个间隙相关联。选择性电路可操作地耦合到多个信号抽头，并且适于从多个信号抽头中的第一和第二信号抽头输出（206）数据。受控电压分量（212）可操作地耦合多个逆变器电路，并且适于提供期望的电源电压。受控信号分量（210）可操作地耦合多个逆变器电路，并且适于向其提供期望频率的信号。评估组件（208）从第一和第二信号抽头接收用于评估或处理的信号数据。

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