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1. 发明授权

US07257788B2 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits 有权
标题翻译：用于将全局时钟选通电路转换为本地时钟门控电路的方法和装置
公开(公告)号：US07257788B2
公开(公告)日：2007-08-14
申请号：US10904397
申请日：2004-11-08
申请人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.
摘要翻译：公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

2. 发明授权

US07000214B2 Method for designing an integrated circuit having multiple voltage domains 失效
标题翻译：用于设计具有多个电压域的集成电路的方法
公开(公告)号：US07000214B2
公开(公告)日：2006-02-14
申请号：US10707068
申请日：2003-11-19
申请人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
摘要翻译：一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

3. 发明授权

US07755420B2 Intrinsic RC power distribution for noise filtering of analog supplies 失效
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

4. 发明申请

US20090024972A1 STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电结构
公开(公告)号：US20090024972A1
公开(公告)日：2009-01-22
申请号：US12163025
申请日：2008-06-27
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

5. 发明申请

US20090021085A1 DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电的设计结构，方法和系统
公开(公告)号：US20090021085A1
公开(公告)日：2009-01-22
申请号：US11866537
申请日：2007-10-03
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H01H37/32
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

6. 发明申请

US20080229265A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229265A1
公开(公告)日：2008-09-18
申请号：US12129748
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F17/5045
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

7. 发明申请

US20080186051A1 FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元
公开(公告)号：US20080186051A1
公开(公告)日：2008-08-07
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/094
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

8. 发明授权

US07898286B2 Critical path redundant logic for mitigation of hardware across chip variation 有权
标题翻译：用于缓解跨芯片变化的硬件的关键路径冗余逻辑
公开(公告)号：US07898286B2
公开(公告)日：2011-03-01
申请号：US12369066
申请日：2009-02-11
申请人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
摘要翻译：用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和绕过每个通过的功能路径。

9. 发明申请

US20090106724A1 Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design 有权
标题翻译：在设计，综合和物理设计过程中减少平衡降噪/减少Di / Dt
公开(公告)号：US20090106724A1
公开(公告)日：2009-04-23
申请号：US11875032
申请日：2007-10-19
申请人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Serafino Bueti , Joseph A. Iadanza , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068
摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
摘要翻译：示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入，移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

10. 发明申请

US20090051420A1 INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES 失效
标题翻译：用于噪声滤波的模拟电源的内部RC功率分配
公开(公告)号：US20090051420A1
公开(公告)日：2009-02-26
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, JR. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

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