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1. 发明授权

US07257788B2 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits 有权
标题翻译：用于将全局时钟选通电路转换为本地时钟门控电路的方法和装置
公开(公告)号：US07257788B2
公开(公告)日：2007-08-14
申请号：US10904397
申请日：2004-11-08
申请人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Allen P. Haar , Joseph A. Iadanza , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.
摘要翻译：公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

2. 发明授权

US07000214B2 Method for designing an integrated circuit having multiple voltage domains 失效
标题翻译：用于设计具有多个电压域的集成电路的方法
公开(公告)号：US07000214B2
公开(公告)日：2006-02-14
申请号：US10707068
申请日：2003-11-19
申请人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
发明人： Joseph A. Iadanza , Raminderpal Singh , Sebastian T. Ventrone , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
摘要翻译：一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

3. 发明授权

US07454305B2 Method and apparatus for storing circuit calibration information 失效
标题翻译：存储电路校准信息的方法和装置
公开(公告)号：US07454305B2
公开(公告)日：2008-11-18
申请号：US11164040
申请日：2005-11-08
申请人： Anthony R. Bonaccio , Allen P. Haar , Joseph A. Iadanza , Douglas W. Stout , Ivan L. Wemple
发明人： Anthony R. Bonaccio , Allen P. Haar , Joseph A. Iadanza , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G01R31/2884 , G01R35/005
摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.
摘要翻译：公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在各个芯片内的存储装置上。然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。内插值与芯片在efuse控制文件中的坐标一起被记录。这样的信息随后被存储在芯片内的efuse模块中。片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

4. 发明授权

US06963240B2 Damping of LC ringing in IC (integrated circuit) power distribution systems 失效
标题翻译： IC（集成电路）配电系统中LC振荡的阻尼
公开(公告)号：US06963240B2
公开(公告)日：2005-11-08
申请号：US10707171
申请日：2003-11-25
申请人： Anthony R. Bonaccio , Allen P. Haar , Michael A. Sorna , Ivan L. Wemple , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Allen P. Haar , Michael A. Sorna , Ivan L. Wemple , Stephen D. Wyatt
IPC分类号： G05F1/10 , G05F3/02 , H03K17/16 , H03L5/00
CPC分类号： G11C5/14 , H01L23/50 , H01L2924/0002 , H03K17/164 , H01L2924/00
摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.
摘要翻译：用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。该结构包括与多个电开关并联电连接的电阻。电阻和电气开关与封装和片上配电电路串联电连接。当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。这用于抑制功率分配LC振铃。之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

5. 发明授权

US07142991B2 Voltage dependent parameter analysis 有权
标题翻译：电压相关参数分析
公开(公告)号：US07142991B2
公开(公告)日：2006-11-28
申请号：US11095327
申请日：2005-03-31
申请人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
发明人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.
摘要翻译：提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。

6. 发明授权

US06631502B2 Method of analyzing integrated circuit power distribution in chips containing voltage islands 有权
公开(公告)号：US06631502B2
公开(公告)日：2003-10-07
申请号：US09683545
申请日：2002-01-16
申请人： Patrick H. Buffet , Joseph N. Kozhaya , Paul D. Montane , Robert A. Proctor , Erich C. Schanzenbach , Ivan L. Wemple
发明人： Patrick H. Buffet , Joseph N. Kozhaya , Paul D. Montane , Robert A. Proctor , Erich C. Schanzenbach , Ivan L. Wemple
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

7. 发明授权

US08015526B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US08015526B2
公开(公告)日：2011-09-06
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

8. 发明授权

US07441213B2 Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof 有权
标题翻译：用于测试电路仿真中初始条件语句的有效性的方法，以及校正其不一致性
公开(公告)号：US07441213B2
公开(公告)日：2008-10-21
申请号：US11307894
申请日：2006-02-27
申请人： Timothy S. Lehner , Richard D. Kimmel , Ali Sadigh , Emrah Acar , Ying Liu , Ivan L. Wemple
发明人： Timothy S. Lehner , Richard D. Kimmel , Ali Sadigh , Emrah Acar , Ying Liu , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce the IC, and detects when specified ICs are inconsistent while preserving critical or fragile ICs when a two DC-pass approach is used. It further correlates the set of consistent ICs thus obtained with an equivalent circuit and simultaneously provides an input for future use. This allows a user to be notified and given a measure of how bad the inconsistencies are. Detecting inconsistencies is achieved either by measuring the holding current or by measuring the voltage drift if the two DC-pass approach is used.
摘要翻译：描述用于在模拟VLSI电路时通常由用户提供的用于验证初始条件（IC）的方法和系统。检测不一致的IC集合，并由其一致的子集替换。该方法选择用于强制IC的Norton或Thevenin电路中的电阻和源值，并在使用两个DC-pass方法时检测指定的IC是否不一致，同时保留关键或易碎IC。它进一步将由此获得的一组一致的IC与等效电路相关联，并同时提供用于将来使用的输入。这允许用户被通知，并给出了不一致的程度。通过测量保持电流或通过使用两个直流通路的方法测量电压漂移来实现检测不一致。

9. 发明授权

US08438520B2 Early decoupling capacitor optimization method for hierarchical circuit design 失效
标题翻译：用于分层电路设计的早期去耦电容优化方法
公开(公告)号：US08438520B2
公开(公告)日：2013-05-07
申请号：US13219813
申请日：2011-08-29
申请人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
发明人： Kurt A. Carlsen , Charles S. Chiu , Umberto Garofano , Ze Gui Pang , Eric W. Tremble , David Toub , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/78 , G06F2217/82
摘要： Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.
摘要翻译：方法，系统，计算机程序等为集成电路的一个区域确定所需数量的去耦电容器和去耦电容器的近似位置。该区域的切换元件被输入到在计算机化设备上运行的仿真程序中。此外，该区域的配电模型被输入到模拟程序中，并且将电源电压压缩目标输入到模拟程序中。当所有开关元件同时切换时，这些方法，系统等产生满足压缩目标所需的去耦电容器的数量。对于每个开关元件，方法，系统等产生特定数量的去耦电容器，以便在仅元件切换时满足压缩，将特定数量的一部分计算为上限，分配总数的分数的去耦电容器到每个开关电路元件，并将去耦电容器总数的一部分放置在电气附近的元件上。

10. 发明授权

US06698008B2 Row-based placement scoring and legalization measure for books with phase shift mask dependencies 失效
标题翻译：具有相移屏蔽依赖性的图书的基于行的布局评分和合法化度量
公开(公告)号：US06698008B2
公开(公告)日：2004-02-24
申请号：US10016207
申请日：2001-10-30
申请人： Kevin W. McCullen , Ivan L. Wemple
发明人： Kevin W. McCullen , Ivan L. Wemple
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/26
摘要： A method and structure for checking legality of books in a phase-shift circuit design mask which arranges the books in rows, determines a book polarity of phase shift mask features of each of the books, sums polarities of the books within each of the rows to produce a row polarity of phase shift mask features of the row, checks whether the row polarity complies with legal requirements of the circuit design, and modifies placement of the books until all of the rows comply with the legal requirements.
摘要翻译：一种用于检查排列书籍的相移电路设计掩模中书籍的合法性的方法和结构，确定每本书的相移掩模特征的书极性，每行中的书籍的极性和和产生行的相移掩模特征的行极性，检查行极性是否符合电路设计的法律要求，并修改书籍的放置，直到所有行符合法律要求。

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