专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090024972A1 STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电结构
公开(公告)号：US20090024972A1
公开(公告)日：2009-01-22
申请号：US12163025
申请日：2008-06-27
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

2. 发明申请

US20090021085A1 DESIGN STRUCTURES, METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 失效
标题翻译：集成电路供电的设计结构，方法和系统
公开(公告)号：US20090021085A1
公开(公告)日：2009-01-22
申请号：US11866537
申请日：2007-10-03
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H01H37/32
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

3. 发明授权

US07716007B2 Design structures of powering on integrated circuit 失效
标题翻译：集成电路供电的设计结构
公开(公告)号：US07716007B2
公开(公告)日：2010-05-11
申请号：US12163025
申请日：2008-06-27
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G01K1/08 , G06F11/00
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

4. 发明授权

US07483806B1 Design structures, method and systems of powering on integrated circuit 失效
标题翻译：集成电路供电的设计结构，方法和系统
公开(公告)号：US07483806B1
公开(公告)日：2009-01-27
申请号：US11866537
申请日：2007-10-03
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F15/00 , G06F11/00
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

5. 发明申请

US20090022203A1 METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 有权
标题翻译：集成电路供电方法与系统
公开(公告)号：US20090022203A1
公开(公告)日：2009-01-22
申请号：US11780530
申请日：2007-07-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, JR. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G01J5/00
CPC分类号： G05D23/20 , G05D23/1934
摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

6. 发明授权

US08016482B2 Method and systems of powering on integrated circuit 有权
标题翻译：集成电路供电方法和系统
公开(公告)号：US08016482B2
公开(公告)日：2011-09-13
申请号：US11780530
申请日：2007-07-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G01K7/01 , G01K17/00 , G01N25/00
CPC分类号： G05D23/20 , G05D23/1934
摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

7. 发明授权

US07898286B2 Critical path redundant logic for mitigation of hardware across chip variation 有权
标题翻译：用于缓解跨芯片变化的硬件的关键路径冗余逻辑
公开(公告)号：US07898286B2
公开(公告)日：2011-03-01
申请号：US12369066
申请日：2009-02-11
申请人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
发明人： Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.
摘要翻译：用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和绕过每个通过的功能路径。

8. 发明授权

US08291357B2 On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations 有权
标题翻译：集成了导体对的片上识别电路，每个导体具有由于工艺变化而基本上随机的短路的机会
公开(公告)号：US08291357B2
公开(公告)日：2012-10-16
申请号：US11869179
申请日：2007-10-09
申请人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Adam J. Courchesne , Kenneth J. Goodnow , Todd E. Leonard , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F9/45
CPC分类号： H01L23/544 , H01L23/5286 , H01L2223/5444 , H01L2924/0002 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.
摘要翻译：公开了片上识别电路的实施例。在一个实施例中，在一个或多个金属化层内形成导体对（例如，金属焊盘，通孔，线）。每对中的导体之间的距离是预先确定的，因此，在已知的跨越芯片线的变化中，存在短路的随机机会（即，大约50/50的几率）。在另一个实施例中，不同的掩模形成第一导体（例如，由变化的距离分隔并具有不同宽度的金属线）和第二导体（例如，通过变化的距离分开并具有相等宽度的金属通孔）。第一和第二导体在芯片之间交替。由于第一导体的分离距离和宽度不同，第二导体的不同间隔距离和随机掩模对准变化，每个第一导体可以短至多达两个第二导体。在每个实施例中，所得到的短路和开路模式可用作片上标识符或私钥。

9. 发明申请

US20090044054A1 DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
标题翻译： DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器
公开(公告)号：US20090044054A1
公开(公告)日：2009-02-12
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G01R31/28
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正衡量关键路径。

10. 发明申请

US20080127216A1 TASK BASED DEBUGGER (TRANSACATION-EVENT-JOB-TRIGGER) 失效
标题翻译：基于任务调度器（交易活动 - 工作触发器）
公开(公告)号：US20080127216A1
公开(公告)日：2008-05-29
申请号：US11461793
申请日：2006-08-02
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Grogory J. Mann , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Grogory J. Mann , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F17/5022 , G06F15/7842 , G06F2217/14
摘要： The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要翻译：本发明的实施例提供了一种用于基于任务的调试器（事务 - 事件 - 作业触发）的装置，方法等。更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。核心连接到链接功能调试逻辑元件的互连结构。每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式