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1. 发明授权

US06631502B2 Method of analyzing integrated circuit power distribution in chips containing voltage islands 有权
公开(公告)号：US06631502B2
公开(公告)日：2003-10-07
申请号：US09683545
申请日：2002-01-16
申请人： Patrick H. Buffet , Joseph N. Kozhaya , Paul D. Montane , Robert A. Proctor , Erich C. Schanzenbach , Ivan L. Wemple
发明人： Patrick H. Buffet , Joseph N. Kozhaya , Paul D. Montane , Robert A. Proctor , Erich C. Schanzenbach , Ivan L. Wemple
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

2. 发明授权

US07496877B2 Electrostatic discharge failure avoidance through interaction between floorplanning and power routing 失效
标题翻译：通过布局规划和电源布线之间的相互作用来避免静电放电故障
公开(公告)号：US07496877B2
公开(公告)日：2009-02-24
申请号：US11202275
申请日：2005-08-11
申请人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
发明人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.
摘要翻译：描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构功率区域约束。创建这些局部电网结构的说明将传递给自动电力布线工具。

3. 发明授权

US07234124B2 Method and apparatus for performing power routing on a voltage island within an integrated circuit chip 失效
标题翻译：用于在集成电路芯片内的电压岛上执行电力布线的方法和装置
公开(公告)号：US07234124B2
公开(公告)日：2007-06-19
申请号：US10980575
申请日：2004-11-03
申请人： Bing Chen , Scott W. Gould , Mark Kwang-Jen Hsu , Patrick M. Ryan , Erich C. Schanzenbach
发明人： Bing Chen , Scott W. Gould , Mark Kwang-Jen Hsu , Patrick M. Ryan , Erich C. Schanzenbach
IPC分类号： G06F17/50 , H01L23/52 , H01L29/40
CPC分类号： G06F17/5077 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N−1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.
摘要翻译：公开了一种在集成电路芯片内的电压岛上执行电力布线的方法。在金属级别1至N-1上为电压岛产生第一电网。然后，在金属电平N及以上产生第二电网。确定第二稳健电网的边界区域。最后，将一组电源的最短距离连接路由到第二个电网。

4. 发明授权

US06861753B1 Method and apparatus for performing power routing on a voltage island within an integrated circuit chip 失效
标题翻译：用于在集成电路芯片内的电压岛上执行电力布线的方法和装置
公开(公告)号：US06861753B1
公开(公告)日：2005-03-01
申请号：US10605569
申请日：2003-10-09
申请人： Bing Chen , Scott W. Gould , Mark Kwang-Jen Hsu , Patrick M. Ryan , Erich C. Schanzenbach
发明人： Bing Chen , Scott W. Gould , Mark Kwang-Jen Hsu , Patrick M. Ryan , Erich C. Schanzenbach
IPC分类号： G06F17/50 , H01L23/528 , H01L29/40
CPC分类号： G06F17/5077 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N−1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.
摘要翻译：公开了一种在集成电路芯片内的电压岛上执行电力布线的方法。在金属级别1至N-1上为电压岛产生第一电网。然后，在金属电平N及以上产生第二电网。确定第二稳健电网的边界区域。最后，将一组电源的最短距离连接路由到第二个电网。

5. 发明授权

US06725439B1 Method of automated design and checking for ESD robustness 有权
标题翻译：自动设计和检查ESD鲁棒性的方法
公开(公告)号：US06725439B1
公开(公告)日：2004-04-20
申请号：US09678742
申请日：2000-10-04
申请人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
发明人： Philip S. Homsinger , Andrew D. Huber , Debra K. Korejwa , William J. Livingstone , Jeannie H. Panner , Erich C. Schanzenbach , Douglas W. Stout , Steven H. Voldman , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
摘要翻译：具有ESD稳健性的集成电路（IC）芯片和IC芯片接线的系统和方法。每个芯片的I / O端口都应用最小导线宽度和最大电阻约束。这些限制被传播到设计中。阵列焊盘连接到位于芯片上的I / O单元。未使用或浮动焊盘可以直接或通过静电放电（ESD）保护装置连接到电源或接地线。还包括耦合在电源和接地或返回线路之间的多电源保护装置（ESDxx）。因此，布线使得ESD保护器件的导线和通孔足够宽，以提供足够的ESD保护。所有的芯片垫都提供了强大的ESD保护。然后可以验证设计。

6. 发明授权

US5631842A Parallel approach to chip wiring 失效
标题翻译：并联接地芯片接线
公开(公告)号：US5631842A
公开(公告)日：1997-05-20
申请号：US400408
申请日：1995-03-07
申请人： Rafik R. Habra , Erich C. Schanzenbach
发明人： Rafik R. Habra , Erich C. Schanzenbach
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.
摘要翻译：在任何后全球物理设计阶段，集成电路芯片并联布线。该芯片首先被分为相邻的托架，其粗糙的布线坐标来自全局布线阶段。接下来，这些托架被分组成托架组，每个托架组包含相邻的非边缘托架组以及与另一个托架组相邻的边框。每个托架组被分配到处理器上的接线任务，以便使用来自全局布线阶段的粗略坐标并行执行托架组的布线。为了实现托架组之间的布线一致性，在边缘托架上协调布线任务。

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