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1. 发明申请

US20130143000A1 Forming Patterned Graphene Layers 有权
标题翻译：形成图案化石墨烯层
公开(公告)号：US20130143000A1
公开(公告)日：2013-06-06
申请号：US13310885
申请日：2011-12-05
申请人： Ali Afzali-Ardakani , Ahmed Maarouf , Glenn J. Martyna , Katherine Saenger
发明人： Ali Afzali-Ardakani , Ahmed Maarouf , Glenn J. Martyna , Katherine Saenger
IPC分类号： B32B33/00 , H01B13/00 , B32B3/00 , B32B38/10 , B82Y30/00
CPC分类号： H01B1/04 , B32B3/00 , B32B3/12 , B32B9/007 , B32B9/041 , B32B15/20 , B32B2307/202 , B32B2307/206 , B32B2457/00 , B82Y30/00 , B82Y40/00 , C01B32/184 , C23F1/02 , H01L21/02527 , H01L21/042 , H01L21/324 , Y10T428/24545 , Y10T428/24851 , Y10T428/24909 , Y10T428/24917
摘要： An apparatus and method for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.
摘要翻译：一种用于在衬底上形成图案化的石墨烯层的装置和方法。一种这样的方法包括在基底上形成碳化物形成金属或含金属合金的至少一个图案化结构，在碳化物形成金属或含金属合金的至少一个图案化结构的顶部上施加石墨烯层在基板上，在环境中在形成碳化物的金属或含金属的合金的至少一个图案化结构的顶部上加热石墨烯层，以去除邻近碳化物形成金属的至少一个图案化结构的石墨烯区域或含金属的合金，以及去除形成碳化物的金属或含金属的合金的至少一个图案化结构，以在衬底上产生图案化的石墨烯层，其中衬底上的图案化石墨烯层提供电子器件的载流子迁移率。

2. 发明授权

US09102118B2 Forming patterned graphene layers 有权
标题翻译：形成图案化石墨烯层
公开(公告)号：US09102118B2
公开(公告)日：2015-08-11
申请号：US13310885
申请日：2011-12-05
申请人： Ali Afzali-Ardakani , Ahmed Maarouf , Glenn J. Martyna , Katherine Saenger
发明人： Ali Afzali-Ardakani , Ahmed Maarouf , Glenn J. Martyna , Katherine Saenger
IPC分类号： B82Y30/00 , B82Y40/00 , B32B3/00 , C01B31/02 , C23F1/02 , H01B13/00 , C01B31/04
CPC分类号： H01B1/04 , B32B3/00 , B32B3/12 , B32B9/007 , B32B9/041 , B32B15/20 , B32B2307/202 , B32B2307/206 , B32B2457/00 , B82Y30/00 , B82Y40/00 , C01B32/184 , C23F1/02 , H01L21/02527 , H01L21/042 , H01L21/324 , Y10T428/24545 , Y10T428/24851 , Y10T428/24909 , Y10T428/24917
摘要： An apparatus and method for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.
摘要翻译：一种用于在衬底上形成图案化的石墨烯层的装置和方法。一种这样的方法包括在基底上形成碳化物形成金属或含金属合金的至少一个图案化结构，在碳化物形成金属或含金属合金的至少一个图案化结构的顶部上施加石墨烯层在基板上，在环境中在形成碳化物的金属或含金属的合金的至少一个图案化结构的顶部上加热石墨烯层，以去除邻近碳化物形成金属的至少一个图案化结构的石墨烯区域或含金属的合金，以及去除形成碳化物的金属或含金属的合金的至少一个图案化结构，以在衬底上产生图案化的石墨烯层，其中衬底上的图案化石墨烯层提供电子器件的载流子迁移率。

3. 发明申请

US20050196917A1 Method for forming a (111) oriented BSTO thin film layer for high dielectric constant capacitors 审中-公开
标题翻译：用于形成用于高介电常数电容器的（111）取向的BSTO薄膜层的方法
公开(公告)号：US20050196917A1
公开(公告)日：2005-09-08
申请号：US10790786
申请日：2004-03-03
申请人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
发明人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L27/10852
摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.
摘要翻译：公开了一种形成具有（111）结构的高电容结晶介电层的方法。在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

4. 发明申请

US20070164337A1 FLIP FERAM CELL AND METHOD TO FORM SAME 有权
标题翻译：翻转毛细胞及其形成方法
公开(公告)号：US20070164337A1
公开(公告)日：2007-07-19
申请号：US11687000
申请日：2007-03-16
申请人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
发明人： James Adkisson , Charles Black , Alfred Grill , Randy Mann , Deborah Neumayer , Wilbur Pricer , Katherine Saenger , Thomas Shaw
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

5. 发明申请

US20060275971A1 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
公开(公告)号：US20060275971A1
公开(公告)日：2006-12-07
申请号：US11406122
申请日：2006-04-18
申请人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/26
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

6. 发明申请

US20060244068A1 Field effect transistor with mixed-crystal-orientation channel and source/drain regions 有权
标题翻译：具有混晶取向沟道和源极/漏极区的场效应晶体管
公开(公告)号：US20060244068A1
公开(公告)日：2006-11-02
申请号：US11116053
申请日：2005-04-27
申请人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
发明人： Joel Desouza , Devendra Sadana , Katherine Saenger , Chun-yung Sung , Min Yang , Haizhou Yin
IPC分类号： H01L27/12
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/7624 , H01L21/823807 , H01L21/8258 , H01L27/0605 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/66636 , H01L29/7833
摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.
摘要翻译：混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET）以半导体方向设置，其对于空穴迁移率是最佳的。本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。可以并入其中可并入这些新的FET的混合基板及其制造方法。

7. 发明申请

US20060154429A1 Method for fabricating low-defect-density changed orientation Si 失效
标题翻译：制造低缺陷密度变化取向Si的方法
公开(公告)号：US20060154429A1
公开(公告)日：2006-07-13
申请号：US11031142
申请日：2005-01-07
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

8. 发明申请

US20050116230A1 Metal carbide gate structure and method of fabrication 失效
标题翻译：金属硬质合金门结构及其制造方法
公开(公告)号：US20050116230A1
公开(公告)日：2005-06-02
申请号：US10722557
申请日：2003-11-28
申请人： Cyril Cabral , Christophe Detavernier , Rajarao Jammy , Katherine Saenger
发明人： Cyril Cabral , Christophe Detavernier , Rajarao Jammy , Katherine Saenger
IPC分类号： H01L21/8238 , H01L27/108 , H01L29/49
CPC分类号： H01L29/4966 , H01L21/823842
摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.
摘要翻译：提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

9. 发明授权

US08030145B2 Back-gated fully depleted SOI transistor 有权
标题翻译：后栅极完全耗尽的SOI晶体管
公开(公告)号：US08030145B2
公开(公告)日：2011-10-04
申请号：US12684225
申请日：2010-01-08
申请人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
发明人： Leland Chang , Brian L. Ji , Arvind Kumar , Amlan Majumdar , Katherine Saenger , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L21/84
CPC分类号： H01L21/2652 , G03F9/7084 , H01L21/26506 , H01L21/2654 , H01L21/26553 , H01L21/2658 , H01L21/6835 , H01L23/544 , H01L29/78648 , H01L2221/68318 , H01L2221/68363 , H01L2221/68377 , H01L2223/54426 , H01L2224/80006 , H01L2224/8013 , H01L2224/802 , H01L2924/01019 , H01L2924/12044 , H01L2924/13091
摘要： A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
摘要翻译：完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

10. 发明申请

US20060258147A1 Method of forming closed air gap interconnects and structures formed thereby 有权
公开(公告)号：US20060258147A1
公开(公告)日：2006-11-16
申请号：US11405287
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

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