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1. 发明申请

US20060275971A1 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics 失效
公开(公告)号：US20060275971A1
公开(公告)日：2006-12-07
申请号：US11406122
申请日：2006-04-18
申请人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Kam-Leung Lee , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/26
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

2. 发明申请

US20080108204A1 AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES 失效
标题翻译：用于混合定向衬底的拟合/调制再结晶方法
公开(公告)号：US20080108204A1
公开(公告)日：2008-05-08
申请号：US11871694
申请日：2007-10-12
申请人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

3. 发明申请

US20060276011A1 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US20060276011A1
公开(公告)日：2006-12-07
申请号：US11142646
申请日：2005-06-01
申请人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/36
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 非ATR区域的去除退火不受沟槽限制。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

4. 发明申请

US20080057684A1 METHOD FOR FABRICATING LOW-DEFECT-DENSITY CHANGED ORIENTATION Si 失效
标题翻译：用于制造低密度变化方位的方法Si
公开(公告)号：US20080057684A1
公开(公告)日：2008-03-06
申请号：US11873928
申请日：2007-10-17
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

5. 发明申请

US20060154429A1 Method for fabricating low-defect-density changed orientation Si 失效
标题翻译：制造低缺陷密度变化取向Si的方法
公开(公告)号：US20060154429A1
公开(公告)日：2006-07-13
申请号：US11031142
申请日：2005-01-07
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

6. 发明申请

US20080106281A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20080106281A1
公开(公告)日：2008-05-08
申请号：US11929754
申请日：2007-10-30
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R31/26
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

7. 发明申请

US20080100318A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20080100318A1
公开(公告)日：2008-05-01
申请号：US11929783
申请日：2007-10-30
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R31/26
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

8. 发明申请

US20070105350A1 DEFECT REDUCTION BY OXIDATION OF SILICON 失效
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20070105350A1
公开(公告)日：2007-05-10
申请号：US11619040
申请日：2007-01-02
申请人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： C30B1/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

9. 发明申请

US20060046528A1 Electrical connector design and contact geometry and method of use thereof and methods of fabrication thereof 失效
标题翻译：电连接器设计和接触几何及其使用方法及其制造方法
公开(公告)号：US20060046528A1
公开(公告)日：2006-03-02
申请号：US10928473
申请日：2004-08-27
申请人： Brian Beaman , George Chiu , Keith Fogel , Paul Lauro , Daniel Morris , Da-Yuan Shih
发明人： Brian Beaman , George Chiu , Keith Fogel , Paul Lauro , Daniel Morris , Da-Yuan Shih
IPC分类号： H01R12/00
CPC分类号： H01R13/2464 , G01R1/06716 , G01R1/06727 , G01R1/07314 , G01R1/07357 , H01R12/714
摘要： A probe or an electrical connector comprises a substrate with a surface having a plurality of electrical contact locations. A shaped elongated electrical conductor has a first end coupled to one of the electrical contact locations and a second end thereof which projects away from the electrical contact location and through an aperture in a sheet of material. The sheet is disposed to be spaced apart from the surface of the substrate. At the second end of the elongated electrical conductor there is a tip structure, which is larger than the aperture in the sheet of material. The tip structure has a pointed portion thereof. The tip structure is disposed against contact locations of a contact surface. The electronic structure is moved towards the contact surface permitting the tip structure to penetrate into the surface of the electrical contact location thereon and to move, wipe, or vibrate across the surface thereof as the shaped elongated electrical conductor flexes as a result of being compressed by the movement of the electronic structure toward the contact surface.
摘要翻译：探针或电连接器包括具有多个电接触位置的表面的基底。成形细长的电导体具有联接到电接触位置之一的第一端和其第二端，其突出远离电接触位置并穿过材料片中的孔。片材被设置成与衬底的表面间隔开。在细长电导体的第二端，有一个尖端结构，其大于该材料片中的孔。尖端结构具有其尖端部分。尖端结构设置成抵靠接触表面的接触位置。电子结构朝向接触表面移动，允许尖端结构穿过其中的电接触位置的表面并且随着成形细长电导体由于被...的压缩而弯曲而在其表面上移动，擦拭或振动电子结构向接触表面移动。

10. 发明申请

US20080106282A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20080106282A1
公开(公告)日：2008-05-08
申请号：US11929899
申请日：2007-10-30
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R1/073
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

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