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    • 8. 发明授权
    • Extended defect sizing range for wafer inspection
    • 晶圆检查扩展缺陷尺寸范围
    • US09091666B2
    • 2015-07-28
    • US13369294
    • 2012-02-09
    • Zhongping CaiYury YuditskyAnatoly RomanovskyAlexander Slobodov
    • Zhongping CaiYury YuditskyAnatoly RomanovskyAlexander Slobodov
    • G01N21/88G01N21/95
    • G01N21/9501
    • Various embodiments for extended defect sizing range for wafer inspection are provided. One inspection system includes an illumination subsystem configured to direct light to the wafer. The system also includes an image sensor configured to detect light scattered from wafer defects and to generate output responsive to the scattered light. The image sensor is also configured to not have an anti-blooming feature such that when a pixel in the image sensor reaches full well capacity, excess charge flows from the pixel to one or more neighboring pixels in the image sensor. The system further includes a computer subsystem configured to detect the defects on the wafer using the output and to determine a size of the defects on the wafer using the output generated by a pixel and any neighboring pixels of the pixel to which the excess charge flows.
    • 提供了用于晶片检查的扩展缺陷尺寸范围的各种实施例。 一个检查系统包括配置成将光引导到晶片的照明子系统。 该系统还包括图像传感器,其被配置为检测从晶片缺陷散射的光并且响应于散射光产生输出。 图像传感器还被配置为不具有防喷射特征,使得当图像传感器中的像素达到满井容量时,过量电荷从图像传感器中的像素流向一个或多个相邻像素。 该系统还包括被配置为使用输出来检测晶片上的缺陷的计算机子系统,并且使用由像素和多余电荷流过的像素的任何相邻像素产生的输出来确定晶片上的缺陷的尺寸。