会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Two-step electrical connector and method using high resistance path for electrostatic discharge
    • 两级电连接器和使用高电阻路径进行静电放电的方法
    • US06905350B1
    • 2005-06-14
    • US10406697
    • 2003-04-03
    • Albert J. WallashKenneth Allen
    • Albert J. WallashKenneth Allen
    • H01R13/53H01R13/648H01R4/58
    • H01R13/6485H01R13/53
    • A method and corresponding structure for establishing an electrical interconnection is disclosed. There are at least two conductors in one embodiment. The first conductor is preferably a static dissipative material, while the second conductor may be of any conventional electrically conductive material (e.g., copper). These two conductors move relative to each other. More specifically, the first conductor is brought into contact with a device having a stored charged. After a certain amount of relative movement between the first and second conductors, and while the first conductor has remained in contact with the device to allow for dissipation of at least a portion of the charge therefrom, the second conductor is then brought into contact with the device.
    • 公开了一种用于建立电互连的方法和相应的结构。 在一个实施例中至少有两个导体。 第一导体优选是静电耗散材料,而第二导体可以是任何常规的导电材料(例如铜)。 这两个导体相对于彼此移动。 更具体地,第一导体与具有存储带电的装置接触。 在第一和第二导体之间的一定量的相对移动之后,并且当第一导体与装置保持接触以允许从其中消耗至少一部分电荷时,然后使第二导体与 设备。
    • 4. 发明授权
    • Silicon chip with an integrated magnetoresistive head mounted on a slider
    • 具有安装在滑块上的集成磁阻头的硅芯片
    • US5587857A
    • 1996-12-24
    • US324841
    • 1994-10-18
    • Steven H. VoldmanAlbert J. WallashReginald B. Wilcox, Jr.
    • Steven H. VoldmanAlbert J. WallashReginald B. Wilcox, Jr.
    • G11B5/39G11B5/31G11B5/40G11B5/48G11B33/12G11B21/21
    • G11B5/40G11B5/3106G11B33/12G11B5/3967G11B5/4806Y10T29/49034Y10T29/49041
    • An MR head has its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to a silicon chip substrate ground potential or to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the wafer level to ultimate completion of individual sliders. At the wafer level a silicon wafer, which contains the integrated circuit devices, is fixedly mounted to a wafer of slider material, such as titanium carbide. A plurality of rows and columns of MR heads are constructed on the silicon wafer adjacent the integrated circuit devices. The composite wafer is then diced into quadrants wherein each quadrant contains rows and columns of sliders with MR heads. Each quadrant is then diced into rows. Each row is then diced into individual sliders, each slider carrying an MR head which is ESD protected.
    • MR磁头具有防止静电放电(ESD)的MR条纹,例如碳化钛。 MR条纹由多个硅集成电路器件保护,这些硅集成电路器件将从MR条纹到ESD芯片衬底接地电位的ESD感应电流或MR头中的较大部件(例如第一和第二屏蔽层)以及线圈层 。 在优选实施例中,集成电路器件和互连构造在单晶硅芯片中。 硅芯片固定地安装在滑块的后缘,并且MR磁头安装在硅芯片的与集成电路器件相邻的后缘。 本发明包括通过将用于制造MR磁头的薄膜技术与用于制造集成电路器件的集成电路技术结合在一起来批量生产滑块的方法。 这些技术在晶圆级别结合到最终完成各个滑块。 在晶片级,包含集成电路器件的硅晶片固定地安装在诸如碳化钛的滑块材料的晶片上。 在与集成电路器件相邻的硅晶片上构造多个行和列MR磁头。 然后将复合晶片切割成象限,其中每个象限包含具有MR磁头的行和列的滑块。 然后将每个象限切成行。 然后将每一行切成单独的滑块,每个滑块承载ESD保护的MR头。