专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06823496B2 Physical design characterization system 有权
标题翻译：物理设计表征系统
公开(公告)号：US06823496B2
公开(公告)日：2004-11-23
申请号：US10063427
申请日：2002-04-23
申请人： Bette L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
发明人： Bette L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
摘要翻译：用于在芯片设计数据中定位和定义分离到特定几何形状或形状配置的过程敏感点的系统，方法和介质。一旦确定了系统过程敏感站点，就会通过设计检查器对物理设计数据进行编码和执行3D设计检查台。产生目标匹配形状并将其嵌入到设计数据中。过程敏感站点的图片，地图和坐标生成并发送到网站库以供参考。

2. 发明授权

US5587857A Silicon chip with an integrated magnetoresistive head mounted on a slider 失效
标题翻译：具有安装在滑块上的集成磁阻头的硅芯片
公开(公告)号：US5587857A
公开(公告)日：1996-12-24
申请号：US324841
申请日：1994-10-18
申请人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
发明人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
IPC分类号： G11B5/39 , G11B5/31 , G11B5/40 , G11B5/48 , G11B33/12 , G11B21/21
CPC分类号： G11B5/40 , G11B5/3106 , G11B33/12 , G11B5/3967 , G11B5/4806 , Y10T29/49034 , Y10T29/49041
摘要： An MR head has its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to a silicon chip substrate ground potential or to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the wafer level to ultimate completion of individual sliders. At the wafer level a silicon wafer, which contains the integrated circuit devices, is fixedly mounted to a wafer of slider material, such as titanium carbide. A plurality of rows and columns of MR heads are constructed on the silicon wafer adjacent the integrated circuit devices. The composite wafer is then diced into quadrants wherein each quadrant contains rows and columns of sliders with MR heads. Each quadrant is then diced into rows. Each row is then diced into individual sliders, each slider carrying an MR head which is ESD protected.
摘要翻译： MR磁头具有防止静电放电（ESD）的MR条纹，例如碳化钛。 MR条纹由多个硅集成电路器件保护，这些硅集成电路器件将从MR条纹到ESD芯片衬底接地电位的ESD感应电流或MR头中的较大部件（例如第一和第二屏蔽层）以及线圈层。在优选实施例中，集成电路器件和互连构造在单晶硅芯片中。硅芯片固定地安装在滑块的后缘，并且MR磁头安装在硅芯片的与集成电路器件相邻的后缘。本发明包括通过将用于制造MR磁头的薄膜技术与用于制造集成电路器件的集成电路技术结合在一起来批量生产滑块的方法。这些技术在晶圆级别结合到最终完成各个滑块。在晶片级，包含集成电路器件的硅晶片固定地安装在诸如碳化钛的滑块材料的晶片上。在与集成电路器件相邻的硅晶片上构造多个行和列MR磁头。然后将复合晶片切割成象限，其中每个象限包含具有MR磁头的行和列的滑块。然后将每个象限切成行。然后将每一行切成单独的滑块，每个滑块承载ESD保护的MR头。

3. 发明授权

US07584077B2 Physical design characterization system 有权
标题翻译：物理设计表征系统
公开(公告)号：US07584077B2
公开(公告)日：2009-09-01
申请号：US10710113
申请日：2004-06-18
申请人： Betty L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
发明人： Betty L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
摘要翻译：用于在芯片设计数据中定位和定义分离到特定几何形状或形状配置的过程敏感点的系统，方法和介质。一旦确定了系统过程敏感站点，就会通过设计检查器对物理设计数据进行编码和执行3D设计检查台。产生目标匹配形状并将其嵌入到设计数据中。过程敏感站点的图片，地图和坐标生成并发送到网站库以供参考。

4. 发明授权

US5559051A Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider 失效
标题翻译：用于制造具有安装在滑块上的集成磁阻头的硅芯片的工艺
公开(公告)号：US5559051A
公开(公告)日：1996-09-24
申请号：US363465
申请日：1994-12-23
申请人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
发明人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
IPC分类号： G11B5/39 , G11B5/31 , G11B5/40 , G11B5/48 , G11B33/12 , H01L21/28 , H01L21/301 , H01L21/304 , H01L21/48
CPC分类号： G11B5/40 , G11B5/3106 , G11B33/12 , G11B5/3967 , G11B5/4806 , Y10T29/49034 , Y10T29/49041
摘要： A process of making an MR head having its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the row level to ultimate completion of individual sliders. A silicon wafer, including the integrated circuit devices, is sliced into a plurality of silicon bars, each bar including a row of circuit devices. A plurality of rows and columns of MR heads are constructed on a ceramic wafer. The ceramic wafer is then also sliced into bars, each bar including a row of MR heads. Each silicon bar is then bonded to a ceramic bar, forming composite bars of MR heads electrically connected to the circuit devices. Each composite bar is then further processed and diced into individual sliders, each slider carrying an MR head which is ESD protected.
摘要翻译：制造具有其MR条纹的MR头的过程，其保护不受诸如碳化钛的滑块上的静电放电（ESD）的影响。 MR条纹由多个硅集成电路器件保护，这些硅集成电路器件将MR感应电流从MR条纹传导到MR头中的较大部件，例如第一和第二屏蔽层和线圈层。在优选实施例中，集成电路器件和互连构造在单晶硅芯片中。硅芯片固定地安装在滑块的后缘，并且MR磁头安装在硅芯片的与集成电路器件相邻的后缘。本发明包括通过将用于制造MR磁头的薄膜技术与用于制造集成电路器件的集成电路技术结合在一起来批量生产滑块的方法。这些技术在行级结合到最终完成各个滑块。包括集成电路器件的硅晶片被切成多个硅棒，每个棒包括一排电路器件。在陶瓷晶片上构造多个行和列的MR磁头。然后将陶瓷晶片切成棒，每个棒包括一排MR头。然后将每个硅棒结合到陶瓷棒，形成电连接到电路装置的MR头的复合棒。然后将每个复合棒进一步处理并切割成各个滑块，每个滑块承载ESD保护的MR头。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式