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1. 发明授权

US09036091B2 Receiver and method of receiving analog and digital television signals 有权
标题翻译：接收机和接收模拟和数字电视信号的方法
公开(公告)号：US09036091B2
公开(公告)日：2015-05-19
申请号：US12986053
申请日：2011-01-06
申请人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
发明人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
IPC分类号： H04N5/44 , H04N5/50 , H04N21/426 , H04N5/46 , H03J1/00
CPC分类号： H04N21/42638 , H03J1/0008 , H04N5/46
摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.
摘要翻译：集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

2. 发明申请

US20120176550A1 Receiver and Method of Receiving Analog and Digital Television Signals 有权
标题翻译：接收器和接收模拟和数字电视信号的方法
公开(公告)号：US20120176550A1
公开(公告)日：2012-07-12
申请号：US12986053
申请日：2011-01-06
申请人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
发明人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
IPC分类号： H04N5/455
CPC分类号： H04N21/42638 , H03J1/0008 , H04N5/46
摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.
摘要翻译：集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

3. 发明授权

US08848110B2 Mixed-mode receiver circuit including digital gain control 有权
标题翻译：混合模式接收机电路包括数字增益控制
公开(公告)号：US08848110B2
公开(公告)日：2014-09-30
申请号：US12790405
申请日：2010-05-28
申请人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
发明人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
IPC分类号： H04N5/52 , H04N5/44 , H04L27/02 , H03G3/30 , H04N5/455 , H03G3/00 , H04L27/00 , H04L27/08 , H04N5/04
CPC分类号： H04N5/455 , H03G3/001 , H03G3/002 , H03G3/3068 , H04L27/0002 , H04L27/02 , H04L27/08 , H04N5/04 , H04N5/52
摘要： A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.
摘要翻译：接收机电路包括模拟前端和数字处理单元。模拟前端包括用于接收射频（RF）信号的输入，用于接收增益调整信号的第一控制输入，用于接收定时信号的第二控制输入和用于提供数字中频的信号输出（ IF）信号。模拟前端根据增益调整信号更新多个增益级的增益并与定时信号同步。数字处理单元被配置为产生从数字IF信号导出的至少一个输出信号。数字处理单元包括定时恢复电路，其被配置为基于数字IF信号生成定时信号，以控制多个可调增益级中的每一个的更新增益的定时。

4. 发明申请

US20110235758A1 Mixed-Mode Receiver Circuit Including Digital Gain Control 有权
标题翻译：包括数字增益控制的混合模式接收器电路
公开(公告)号：US20110235758A1
公开(公告)日：2011-09-29
申请号：US12790405
申请日：2010-05-28
申请人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
发明人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
IPC分类号： H04L27/08 , H04B1/06 , H04N5/08
CPC分类号： H04N5/455 , H03G3/001 , H03G3/002 , H03G3/3068 , H04L27/0002 , H04L27/02 , H04L27/08 , H04N5/04 , H04N5/52
摘要： A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.
摘要翻译：接收机电路包括模拟前端和数字处理单元。模拟前端包括用于接收射频（RF）信号的输入，用于接收增益调整信号的第一控制输入，用于接收定时信号的第二控制输入和用于提供数字中频的信号输出（ IF）信号。模拟前端根据增益调整信号更新多个增益级的增益并与定时信号同步。数字处理单元被配置为产生从数字IF信号导出的至少一个输出信号。数字处理单元包括定时恢复电路，其被配置为基于数字IF信号生成定时信号，以控制多个可调增益级中的每一个的更新增益的定时。

5. 发明授权

US08385867B2 Tracking filter for a television tuner 有权
标题翻译：电视调谐器的跟踪滤波器
公开(公告)号：US08385867B2
公开(公告)日：2013-02-26
申请号：US12493819
申请日：2009-06-29
申请人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
发明人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
IPC分类号： H04B1/18
CPC分类号： H03J3/06 , H03J3/32 , H03J2200/10 , H03J2200/32 , H04N5/50
摘要： In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.
摘要翻译：在一个实施例中，提供要耦合在放大器和混频器之间的一组跟踪滤波器。根据操作频带，跟踪滤波器可以被不同地配置。例如，可以将第一组滤波器配置为在其工作带宽上维持基本上恒定的Q值，而第二组滤波器可被配置为在其工作带宽上维持基本恒定的带宽。

6. 发明申请

US20100328546A1 Tracking Filter For A Television Tuner 有权
标题翻译：电视调谐器的跟踪滤波器
公开(公告)号：US20100328546A1
公开(公告)日：2010-12-30
申请号：US12493819
申请日：2009-06-29
申请人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
发明人： Aslamali A. Rafi , Chunyu Xin , Ruifeng Sun , Abhishek Kammula , Ramin Khoini-Poorfard , Alessandro Piovaccari , Peter J. Vancorenland
IPC分类号： H04N5/50 , H04B1/10 , H04B1/06
CPC分类号： H03J3/06 , H03J3/32 , H03J2200/10 , H03J2200/32 , H04N5/50
摘要： In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.
摘要翻译：在一个实施例中，提供要耦合在放大器和混频器之间的一组跟踪滤波器。根据操作频带，跟踪滤波器可以被不同地配置。例如，可以将第一组滤波器配置为在其工作带宽上维持基本上恒定的Q值，而第二组滤波器可被配置为在其工作带宽上维持基本恒定的带宽。

7. 发明授权

US09647623B2 Signal processor suitable for low intermediate frequency (LIF) or zero intermediate frequency (ZIF) operation 有权
公开(公告)号：US09647623B2
公开(公告)日：2017-05-09
申请号：US12571092
申请日：2009-09-30
申请人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
发明人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
IPC分类号： H04B1/06 , H03G3/30
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.

8. 发明授权

US08428536B2 Low-cost receiver using automatic gain control 有权
标题翻译：低成本接收机采用自动增益控制
公开(公告)号：US08428536B2
公开(公告)日：2013-04-23
申请号：US12323040
申请日：2008-11-25
申请人： Ramin Khoini-Poorfard , Alessandro Piovaccari , David S. Trager
发明人： Ramin Khoini-Poorfard , Alessandro Piovaccari , David S. Trager
IPC分类号： H04B1/06 , H04B7/00 , H04L27/08
CPC分类号： H04B1/28 , H03G3/3068
摘要： A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.
摘要翻译：接收器（100）包括具有信号输入的第一元件（110），控制输入，信号输出和第一幅度的增益步长，信号处理电路（120-168），信号输入端与第一元件和信号输出，具有耦合到信号处理电路的信号输入的第二元件（180），小于第一幅度的第二幅度的控制输入，信号输出和增益步骤，以及控制器（180）），其具有耦合到所述第一元件（110）的控制输出，耦合到所述第二元件（180）的控制输出，并且通过将所述第一元件（110）增益改变第一量值来调整接收器（100）增益，第二元件（180）通过基本上相反的第一幅度增益，随后通过第二幅度的步长来改变第二元件（180）的增益，以实现期望的增益。

9. 发明申请

US20110076977A1 Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation 有权
标题翻译：信号处理器适用于低中频（LIF）或零中频（ZIF）操作
公开(公告)号：US20110076977A1
公开(公告)日：2011-03-31
申请号：US12571092
申请日：2009-09-30
申请人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
发明人： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin Khoini-Poorfard , James T. Kao
IPC分类号： H04B1/06
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
摘要翻译：一种用于射频（RF）接收机的信号处理器包括多个分布式信号处理元件，其中第一个接收输入信号，最后一个提供输出信号，并且多个增益元素散布在所述多个的分布式信号处理元件。信号处理器还包括耦合到所述多个增益元件中对应的增益元件的相应输出端的相同的多个峰值检测器，以及具有耦合到每个峰值检测器的输出的输入的自动增益控制器，以及耦合到多个获得元素。自动增益控制器独立地控制多个增益元件中的每一个以形成相同的多个独立的自动增益控制（AGC）回路。

10. 发明申请

US20130335639A1 Configurable Buffer For An Integrated Circuit 有权
标题翻译：用于集成电路的可配置缓冲器
公开(公告)号：US20130335639A1
公开(公告)日：2013-12-19
申请号：US13526060
申请日：2012-06-18
申请人： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
发明人： András Vince Horvath , Abdulkerim L. Coban , Pio Balmelli , Ramin Khoini-Poorfard , Alessandro Piovaccari
IPC分类号： H03L5/00 , H04N5/50
CPC分类号： H04N5/50 , H03J5/24 , H04L25/0292 , H04N5/165 , H04N5/455 , H04N21/42607
摘要： In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.
摘要翻译：在一个实施例中，内部缓冲器可以设置在集成电路（IC）内，以在开关的控制下将信号转换成经由IC的引脚输出的输出电流，该开关可以基于配置设置 IC，并且当IC耦合到外部驱动器电路时，可以选择性地将信号耦合到引脚。

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