专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09036091B2 Receiver and method of receiving analog and digital television signals 有权
标题翻译：接收机和接收模拟和数字电视信号的方法
公开(公告)号：US09036091B2
公开(公告)日：2015-05-19
申请号：US12986053
申请日：2011-01-06
申请人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
发明人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
IPC分类号： H04N5/44 , H04N5/50 , H04N21/426 , H04N5/46 , H03J1/00
CPC分类号： H04N21/42638 , H03J1/0008 , H04N5/46
摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.
摘要翻译：集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

2. 发明申请

US20120176550A1 Receiver and Method of Receiving Analog and Digital Television Signals 有权
标题翻译：接收器和接收模拟和数字电视信号的方法
公开(公告)号：US20120176550A1
公开(公告)日：2012-07-12
申请号：US12986053
申请日：2011-01-06
申请人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
发明人： Alan F. Hendrickson , Alessandro Piovaccari , Ramin Khoini-Poorfard , Mitchell Reid , Frederick Alan Rush , Jean-Marc Guyot , David Le Goff , Michael Robert May , Henry William Singor , Qi Cai , Peter Jozef Vancorenland , Chunyu Xin , Pascal Blouin
IPC分类号： H04N5/455
CPC分类号： H04N21/42638 , H03J1/0008 , H04N5/46
摘要： An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.
摘要翻译：集成电路包括调谐器，数字电视（DTV）解调器，模拟电视（ATV）解调器和控制器。调谐器包括用于接收包括模拟电视信号和数字电视信号中的至少一个的射频（RF）信号的输入，并且包括第一输出端和第二输出端。 DTV解调器包括耦合到调谐器的第一输出端的DTV输入，并且包括DTV输出端。 ATV解调器包括耦合到调谐器的第二输出端子的ATV输入并且包括ATV输出端子。控制器耦合到调谐器，DTV解调器和ATV解调器，以配置调谐器和至少一个DTV解调器和ATV解调器，用于以选定的电视格式接收电视内容。

3. 发明申请

US20110115537A1 CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL 有权
标题翻译：用于重新插入输入信号的电路装置和方法
公开(公告)号：US20110115537A1
公开(公告)日：2011-05-19
申请号：US12621050
申请日：2009-11-18
申请人： Michael Robert May , Russell Croman , Younes Djadi , Scott Thomas Haban
发明人： Michael Robert May , Russell Croman , Younes Djadi , Scott Thomas Haban
IPC分类号： H03K5/12
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译：实施例包括用于对输入信号进行重新计时的电路装置和方法。在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。

4. 发明申请

US20110158298A1 TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME 审中-公开
标题翻译：具有片间传输器的调谐电路和提供互连链路帧的方法
公开(公告)号：US20110158298A1
公开(公告)日：2011-06-30
申请号：US12649911
申请日：2009-12-30
申请人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
发明人： Younes Djadi , Russell Croman , Scott Thomas Haban , Javier Elenes , Gerald Champagne , Michael Robert May
IPC分类号： H04B1/38 , H04L27/00
CPC分类号： H04B1/38
摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.
摘要翻译：调谐器电路包括数字信号处理器，用于产生与射频信号相关的数字数据流，以及耦合到数字信号处理器的收发器电路，并且可配置为产生具有起始部分和多个通道的芯片间通信帧。多个信道包括携带数字数据流的一部分的第一数据信道和用于携带控制数据的控制信道。收发器电路可配置为通过芯片间通信链路将片间通信帧发送到附加的调谐器电路。

5. 发明申请

US20110115556A1 CIRCUIT DEVICES AND METHODS OF PROVIDING A REGULATED POWER SUPPLY 有权
标题翻译：提供调节电源的电路设备和方法
公开(公告)号：US20110115556A1
公开(公告)日：2011-05-19
申请号：US12620669
申请日：2009-11-18
申请人： Michael Robert May
发明人： Michael Robert May
IPC分类号： G05F1/10
CPC分类号： G05F1/618
摘要： In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply.
摘要翻译：在一个实施例中，电路包括调节电源端子，耦合到稳压电源端子的处理电路和具有适于耦合到电源的第一晶体管的低频响应电路，并且具有被配置为控制电流的第一电路从电源流经第一晶体管，向稳压电源端子提供低频电流。电路装置还包括高频响应电路，其具有耦合到稳压电源端的第二晶体管，并具有第二电路，其被配置为控制第二晶体管以选择性地调制稳压电源端子处的高频电流分量，以减小电压变化稳压电源。

6. 发明授权

US09041452B2 Circuit and method of clocking multiple digital circuits in multiple phases 有权
标题翻译：多个时钟多个数字电路的电路和方法
公开(公告)号：US09041452B2
公开(公告)日：2015-05-26
申请号：US12694630
申请日：2010-01-27
申请人： Michael Robert May , David S. Trager
发明人： Michael Robert May , David S. Trager
IPC分类号： H03K3/00 , G06F1/06 , H03K3/84 , G06F1/10
CPC分类号： G06F1/06 , G06F1/10 , H03K3/84
摘要： A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
摘要翻译：电路包括电源端子和时钟解析电路，其被配置为产生具有公共时钟周期和不同相位的多个时钟信号。电路还包括耦合到时钟解析电路和电源端的多个数字电路。每个数字电路包括用于接收数据和用于处理数据的逻辑的输入。每个数字电路响应于与多个时钟信号的相应时钟信号相关联的相位，以从调节电源端子抽取电流来处理数据以产生数据输出。另外，电路包括耦合到多个数字电路中的每一个并被配置为控制多个数字电路中的每一个的数据输出的输出定时管理电路，以防止在一个或多个目的地电路处的定时违反。

7. 发明申请

US20110181325A1 CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES 有权
标题翻译：在多个相位中定时切换多个数字电路的电路和方法
公开(公告)号：US20110181325A1
公开(公告)日：2011-07-28
申请号：US12694630
申请日：2010-01-27
申请人： Michael Robert May , David S. Trager
发明人： Michael Robert May , David S. Trager
IPC分类号： H03L7/00
CPC分类号： G06F1/06 , G06F1/10 , H03K3/84
摘要： A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.
摘要翻译：电路包括电源端子和时钟解析电路，其被配置为产生具有公共时钟周期和不同相位的多个时钟信号。电路还包括耦合到时钟解析电路和电源端的多个数字电路。每个数字电路包括用于接收数据和用于处理数据的逻辑的输入。每个数字电路响应于与多个时钟信号的相应时钟信号相关联的相位，以从调节电源端子抽取电流来处理数据以产生数据输出。另外，电路包括耦合到多个数字电路中的每一个并被配置为控制多个数字电路中的每一个的数据输出的输出定时管理电路，以防止在一个或多个目的地电路处的定时违反。

8. 发明授权

US08564256B2 Circuit devices and methods of providing a regulated power supply 有权
标题翻译：提供稳压电源的电路装置和方法
公开(公告)号：US08564256B2
公开(公告)日：2013-10-22
申请号：US12620669
申请日：2009-11-18
申请人： Michael Robert May
发明人： Michael Robert May
IPC分类号： G05F1/613 , G05F1/40
CPC分类号： G05F1/618
摘要： In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply.
摘要翻译：在一个实施例中，电路包括调节电源端子，耦合到稳压电源端子的处理电路和具有适于耦合到电源的第一晶体管的低频响应电路，并且具有被配置为控制电流的第一电路从电源流经第一晶体管，向稳压电源端子提供低频电流。电路装置还包括高频响应电路，其具有耦合到稳压电源端的第二晶体管，并具有第二电路，其被配置为控制第二晶体管以选择性地调制稳压电源端子处的高频电流分量，以减小电压变化稳压电源。

9. 发明授权

US6081216A Low-power decimator for an oversampled analog-to-digital converter and method therefor 失效
标题翻译：用于过采样模数转换器的低功耗抽取器及其方法
公开(公告)号：US6081216A
公开(公告)日：2000-06-27
申请号：US96049
申请日：1998-06-11
申请人： Michael Robert May
发明人： Michael Robert May
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/462 , H03M3/32
摘要： An oversampled analog-to-digital converter (ADC) (20) includes a sigma-delta modulator (21) with two decimation filters to provide minimum power consumption. The first decimation filter (30) converts the output of the sigma-delta modulator (21) to a slower intermediate frequency and performs a first part of the decimation function. The second decimation filter (40) converts the output of the first decimation filter (30) to the output frequency and performs a second part of the decimation function. The ADC (20) saves power by allowing some of the second part of the decimation function to be performed at the slower intermediate frequency. In one form, the first decimation filter (30) includes a finite impulse response (FIR) filter (32) and a down sampler (34). By using a suitable logic circuit (56), the FIR filter (32) can be implemented with only a small amount of circuit area and most of the FIR filter (32) can be operated at the slower intermediate frequency.
摘要翻译：过采样模数转换器（ADC）（20）包括具有两个抽取滤波器以提供最小功耗的Σ-Δ调制器（21）。第一抽取滤波器（30）将Σ-Δ调制器（21）的输出转换成较慢的中频，并执行抽取功能的第一部分。第二抽取滤波器（40）将第一抽取滤波器（30）的输出转换为输出频率，并执行抽取功能的第二部分。 ADC（20）通过允许在较慢的中频执行抽取功能的第二部分中的一些来节省功率。在一种形式中，第一抽取滤波器（30）包括有限脉冲响应（FIR）滤波器（32）和下采样器（34）。通过使用合适的逻辑电路（56），FIR滤波器（32）可以仅用少量的电路面积来实现，并且FIR滤波器（32）的大部分可以在较慢的中间频率下操作。

10. 发明授权

US09209912B2 Circuit devices and methods for re-clocking an input signal 有权
标题翻译：用于重新输入信号的电路设备和方法
公开(公告)号：US09209912B2
公开(公告)日：2015-12-08
申请号：US12621050
申请日：2009-11-18
申请人： Michael Robert May , Russell Croman , Younes Djadi , Scott Thomas Haban
发明人： Michael Robert May , Russell Croman , Younes Djadi , Scott Thomas Haban
IPC分类号： H04L7/00 , H04B15/04
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/065 , H04L7/0045 , H04L7/0091
摘要： Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.
摘要翻译：实施例包括用于对输入信号进行重新计时的电路装置和方法。在一个实施例中，电路设备包括具有数据输入的数据存储元件，用于接收具有第一时钟速率的数字数据流并且包括时钟输入以接收具有第二时钟速率的时钟信号。数据存储元件还包括基于时钟信号来调整数字数据流内的转换的边沿定时的逻辑，以产生具有在期望频率下具有频谱零点的功率谱的调制输出信号及其谐波而不改变平均数据速率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式